Renesas M16C/50 Series User Manual page 641

M16C/5L Group, M16C/56 Group
23.3 CAN Communication Speed Configuration
The following description explains about the CAN communication speed configuration.
23.3.1 CAN Clock Configuration
This group has a CAN clock selector.
The CAN clock can be configured by setting the CCLKS bit in the C0CLKR register and the BRP bit in
the C0BCR register.
Figure 23.36 shows the block diagram of CAN clock generator.
Main clock
CCLKS: Bit in C0CLKR register
fCAN: CAN clock
P: Value selected using BRP bit in C0BCR register, P = 0 to 1023
fCANCLK: CAN communication clock, fCANCLK = fCAN / (P + 1)
Figure 23.36 Block Diagram of CAN Clock Generator
23.3.2 Bit Timing Configuration
The bit time is a single bit time for transmitting/receiving a message and consists of the following three
segments.
Figure 23.37 shows the bit timing.
Range of each segment:
Setting of TSEG1 and TSEG2: TSEG1 > TSEG2 > SJW
Figure 23.37 Bit Timing
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
CCLKS
0
BCLK
fCAN
1
SS TSEG1
Bit time = 8 Tq to 25 Tq
SS = 1 Tq
TSEG1 = 4 Tq to 16 Tq
TSEG2 = 2 Tq to 8 Tq
SJW = 1 Tq to 4 Tq
fCANCLK
Baud rate prescaler
division value: P + 1
P = 0 to 1023
Bit time
Sample point
23. CAN Module
TSEG2
Page 604 of 803