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REVISION HISTORY
Rev.
Date
0.70
Oct. 09, 2009
Processor Mode
Programmable I/O Ports
Interrupts
Watchdog Timer
DMAC
Timer A
Timer B
M16C/5L Group, M16C/56 Group Hardware Manual
Page
141
Table 9.7 "Resets and Interrupts to Exit Wait Mode and Usage Conditions" partially modified
144
Table 9.9 "Resets and Interrupts to Exit Stop Mode and Usage Conditions" partially modified
146
Figure 9.2 "Setting Procedures to Stop and Restart the Flash Memory" partially modified
150
9.7.2 "Wait Mode" partially modified
153
Table 10.2 "Register List" partially modified
155
Processor Mode Register 2 (PM2) deleted
155
10.2.3 "Flash Memory Control Register 1 (FMR1)" note deleted
155
"FMR17 (Data Flash Wait Bit) (b7)" modified
156
Table 10.3 "Software Wait Related Bits and Bus Cycles" partially modified
11.3.7 "Input Threshold Select Register 0 (VLT0)" to 11.3.9 "Input Threshold Select Register 2
169-170
(VLT2)" register name "Input Thereshold Control Register" changed to "Input Thereshold
Select Register"
171
11.3.10 "Pin Assignment Control Register (PACR)" note deleted
172
11.3.11 "Port Pi Registers (Pi) (i = 0 to 10)" partially modified
184
Table 12.5 "Register List (3)" 02F0h, 02F1h, and 02F2h deleted
"PM24 ( NMI Interrupt Enable Bit) (b4)" partially modified
185
193
Port Control Register (PCR) deleted
193
12.2.11 "P1_7 Digital Debounce Register (P17DDR)" added
197
Table 12.6 "Fixed Vector Tables" partially modified
Table 12.7 "Relocatable Vector Tables (1/2)" and Table 12.8 "Relocatable Vector Tables (2/2)"
198-199
"INT instruction interrupt" moved
12.9 " NMI Interrupt" partially modified
209
210
12.10 "Key Input Interrupt" and Figure 12.10 "Key Input Interrupt" partially modified
12.13.3 " NMI Interrupt" some description added
213
215
12.13.5 "Rewriting the Interrupt Control Register" partially modified
215
12.13.6 "Instruction to Rewrite the Interrupt Control Register" added
13.2.1 "Voltage Monitor 2 Circuit Control Register (VW2C)" description "(excluding the VW2C3
220
bit)" added
222
13.2.1 "Voltage Monitor 2 Circuit Control Register (VW2C)" partially modified
243
Table 14.8 "DMAC Transfer Cycles" description for DMBIT added
267
15.3.1.3 "Count Source" partially modified
269
Table 15.7 "Registers and the Setting in Timer Mode
Table 15.9 "Registers and the Setting in Event Counter Mode (When Not Processing Two-
273
Phase Pulse Signal)
275
Figure 15.6 "Operation Example in Event Counter Mode" set value of the TAi register added
Table 15.11 "Registers and the Setting in Event Counter Mode (When Processing Two-Phase
277
(1)
Pulse Signal)
" bit for TAi1 and TAi modified
280
15.3.4.3 "Counter Initialization by Two-Phase Pulse Signal Processing" modified
Table 15.13 "Registers and the Settings in One-Shot Timer Mode
282
modified
Table 15.15 "Registers and Settings in Pulse Width Modulation Mode
286
modified
Table 15.17 "Registers and Settings in Programmable Output Mode
291
register TAOW added
16.2.5 "Pulse Period/Pulse Width Measurement Mode Function Select Register 1 (PPWFS1)"
306
partially modified
Revision History
(1)
" bit for TAi1 and TAi modified
C- 18
(1)
" bit for TAi1 and TAi modified
(1)
" bit for TAi1 and TAi
(1)
" bit for TAi1 and TAi
(1)
" bit for TAi1 and TAi;
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