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M16C/5L Group, M16C/56 Group
When setting the WIT bit to 1 in receive mode, and the ACK clock is present:
2
(I
C-bus interrupt is enabled at eighth clock)
SCLMM
SDAMM
ACKBIT bit in the
S20 register
PIN bit in the S10 register
Internal WAIT flag
IR bit in the IICIC register
Write signal to the
S00 register
When setting the WIT bit to 0 in receive mode, and the ACK clock is present:
2
(I
C-bus interrupt is disabled at eighth clock)
SCLMM
SDAMM
ACKBIT bit in the
S20 register
PIN bit in the S10 register
Internal WAIT flag
IR bit in the IICIC register
Write signal to the
S00 register
Figure 22.4
Interrupt Request Generation Timing in Receive Mode
SDAM (Internal SDA output monitor bit) (b4)
SCLM (Internal SCL output monitor bit) (b5)
The internal SDA and SCL output signal levels are the same as the output level of the I
before it has any effect from the external device output. Bits SDAM and SCLM are read only bits. If
necessary, set these bits to 0.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
7
8
Write by a program
Set to 0 by an interrupt acceptance or by a program
7
8
0
0
Set to 0 by an interrupt acceptance or
by a program
22. Multi-master I
9
ACK
clock
(1)
9
ACK
clock
ACK bit
(2)
2
C-bus Interface
(2)
1
2
C interface
Page 512 of 803
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