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REVISION HISTORY
Rev.
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1.10 Sep. 01, 2011
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Real-Time Clock
Chap. 20. Changed "compare x mode" to "compare mode x".
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Serial Interface UARTi
Chap. 21. Changed the configuration. The orders of tables or sections possibly changed, accordingly.
Chap. 21. 21.3.3.6 SDA Output Control to 21.3.3.10 Initialization of Transmission/Reception: Revised.
Chap. 21. 21.8.2 Clock Asynchronous Serial I/O Mode (UART Mode): Deleted.
Chap. 21.
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M16C/5L, M16C/56 Group User's Manual: Hardware
Figure 18.14 Single-Phase Waveform Output Mode Operation (1/2):
Changed "fBTi" to "fBT1" in (1).
Figure 18.15 Single-Phase Waveform Output Mode Operation (2/2):
• Added "when bits IOj1 and IOj0 are 10b" to the description "Output high by compare match".
• Added a condition regarding the EOCj bit in the G1OER register.
18.3.3.2 Inverted Waveform Output Mode:
Rewrote the explanation for when the inverted waveform output mode is set.
Table 18.14 Inverted Waveform Output Mode Specifications:
• Changed the range of values for m and n.
• Changed the Interrupt request to the Interrupt request occurrence timing in the Item column.
• Added "or I/O port" to the Specification of the OUTC1_ j pin.
Table 18.15 Registers and Settings in Inverted Waveform Output Mode: Added.
Figure 18.17 Inverted Waveform Output Mode Operation (2/2):
• Added "when bits IOj1 and IOj0 are 10b" to the description "Output high by compare match".
18.3.3.3 Set/Reset Waveform Output Mode (SR Waveform Output Mode):
• Changed "G1POCRi register (i = 0 to 7)" to "G1POCRj register (j = 0, 2, 4, 6)" in line 1.
• Added "and G1POCRk" to line 4.
Table 18.16 SR Waveform Output Mode Specifications:
• Changed the range of values for m, n and p.
• Changed the Interrupt request to the Interrupt request occurrence timing in the Item column.
• Added "or I/O port" to the Specification of the OUTC1_ j pin.
• Rewrote the description of the Output disabled in the Specifications column of the Selectable
functions row.
Table 18.17 Registers and Settings in SR Waveform Output Mode: Added.
18.3.4 "I/O Port Select Function":
Rewrote the contents of "18.6.1 INPC1_7 Alternate Input Pin" and "18.6.2 P1_7/INPC1_7 Digital
Debounce Function", and moved here.
Table 18.18 Pin Settings for Time Measurement and Waveform Generation: Simplified.
18.4 Interrupts: Changed.
18.5.1 Register Access: Added.
18.5.2 Changing the G1IR Register: Changed the title from "G1IR Register", and changed the
explanation.
Figure 18.20 IC/OC Interrupt 0 Operation Example: Changed from "IC/OC Interrupt 0 and 1
Operation".
18.5.3 Changing Registers ICOCiIC (i = 0, 1): Changed from "Registers ICOCiIC and ICOCHjIC".
18.5.4 Output Waveform During the Base Timer Reset with the BTS bit and 18.5.5 OUTC1_0 Pin
Output During the Base Timer Reset with the G1PO0 register: Changed from "Waveform
Generation Function".
18.5.6 Interrupt Request When Selecting Time Measurement Function: Added.
Table 20.1 Real-Time Clock Specifications:
Changed "timer stops" to "count stopped" in the Specification column of the Write to timer row.
Changed terminologies in this chapter are as follows:
• "transfer clock" to "transmit/receive clock"
• "transfer data length" to "character length"
• "transfer data format" to "bit order"
21.1 Introduction: Changed the layout of the introduction, including tables.
Figure 21.2 UARTi Transmit/Receive Unit Block Diagram:
• Unified data buses for low/high-order bits with a single data bus.
• Deleted CKDIR from the explanation about bits.
21.2.3 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 4):
Added an explanation to bits SMD2 to SMD0 for when the bits are set to 000b.
21.2.4 UARTi Bit Rate Register (UiBRG) (i = 0 to 4): Changed the Setting Range.
Description
Summary
C- 9
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