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M16C/5L Group, M16C/56 Group
(3) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit in
the G1BCR0 register are all 0).
Base timer
OUTC1_ j pin
IOj1 bit
IOj0 bit
G1IRj bit
j = 0 to 7
m: G1POj register value
IOj1 and IOj0: Bits in registers G1IOR1 and G1IOR0
G1IRj: Bit in the G1IR register
The above assumes the following:
⋅ IVL bit in the G1POCRj register is 0 (output low as default) and the INV bit is 0 (output is not inverted).
⋅ EOCj bit in the G1OER register is 0 (output enabled).
(4) When the base timer matches either of following registers, the base timer is reset:
(a) G1PO0 register (when the RST1 bit is 1 and bits RST4 and RST2 are 0)
(b) G1BTRR register (when the RST4 bit is 1 and bits RST2 and RST1 are 0)
Base timer
OUTC1_ j pin
IOj1 bit
IOj0 bit
G1IRj bit
When (a), j = 1 to 7. When (b), j = 0 to 7.
m: G1POj register value
n: G1PO0 register or G1BTRR register setting value
G1IRj: Bit in the G1IR register
The above assumes the following:
⋅ The IVL bit in the G1POCRj register is 0 (output low as default) and the INV bit is 0 (output is not inverted).
⋅ The EOCj bit in the G1OER register is 0 (output enabled).
Figure 18.15 Single-Phase Waveform Output Mode Operation (2/2)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
FFFFh
m
0000h
Output high
Output low
0
To set this bit to 0, write 0 by a program
FFFFh
n + 1
m
Output high
Output low
0
To set this bit to 0, write 0 by a program
Output high by compare match
when bits IOj1 and IOj0 are 10b.
Output high by compare match
when bits IOj1 and IOj0 are 10b.
18. Timer S
Output high
Output low
Output high
Output low
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