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2.
Items revised or added in previous versions
REVISION HISTORY
Rev.
Date
0.61
Jul. 31, 2009
0.70
Oct. 09, 2009
The manual in general
SFR Quick Reference
Overview
Special Function Registers (SFRs)
Resets
Voltage Detector
Clock Generator
Power Control
M16C/5L Group, M16C/56 Group Hardware Manual
Page
—
Initial release
—
Description for M16C/56 Group added
—
03A2h "Open-Circuit Detection Assist Function Register" reset value modified
0075h register name "CAN0 Successful Receive Interrupt Control Register" changed to
—
"CAN0 Receive Completion Interrupt Control Register"
0076h register name "CAN0 Successful Transmit Interrupt Control Register" changed to
—
"CAN0 Transmit Completion Interrupt Control Register"
B-3
0140h to 0147h "Register 0 to 3" modified
B-4
0152h "A/D1 Trigger Control Register" modified
B-4
0154h, 0156h, and 0157h "A/D1 Control Register 2, 0, and 1" modified
4
Table 1.3 "Specifications (64-pin Package) (1/2)" partially modified
Figure 1.5 "Pin Assignment for 80-Pin Package (Top View)" and Figure 1.6 "Pin Assignment
10, 13
for 64-Pin Package (Top View)" partially modified
10
1.5 "Pin Assignments" partially modified
23
Table 4.1 SFR List (1) reset value for VCR1 modified
35
Table 4.13 SFR List (13) reset value for FMR0 modified
38
Table 4.16 SFR List (16) reset values for S1D0 and S4D0 modified
45-57
Table 4.23 SFR List (23) to Table 4.35 SFR List (35) reset values modified
60
Table 4.38 SFR List (38) reset values for C0BCR, C0MSMR, C0TSR, and C0AFSR modified
72
Figure 6.3 "Reset Sequence" partially modified
79
Table 7.2 "Register List" reset value for VCR1 modified
79
Table 7.2 "Register List" notes 4 and 5 added
80
7.2.1 "Voltage Detection 2 Circuit Flag Register (VCR1)" reset value modified
7.2.6 "Voltage Monitor 2 Circuit Control Register (VW2C)" description "(excluding the VW2C3
85
bit)" added
90
Table 7.5 "Steps to Set Voltage Monitor 0 Reset Related Bits" partially modified
Figure 7.4 "Voltage Monitor 0 Reset Operation Example" description "Oscillation stop
90
detection interrupt signal" modified to "Oscillation stop/restart detection interrupt signal"
92
Table 7.6 "Steps to Set Voltage Monitor 2 Interrupt/Reset Related Bits" Step 4 added
104
"CM14 (125 kHz On-Chip Oscillator Stop Bit) (b4)" partially modified
106
"CM22 (Oscillation stop/restart detect flag) (b2)" partially modified
114
8.3.3 "fOCO40M" description "td(OCOF)" changed to "tsu (fOCO40M)"
8.3.5 "125-kHz On-Chip Oscillator Clock (fOCO-S)" partially modified; "tosc(OCOF)" changed
115
to "tsu (fOCO-S)"
116
8.3.6 "Sub Clock (fC)" partially modified
116
Figure 8.4 "Sub Clock Circuit Connection" modified
117
8.4.2 "Peripheral Clocks (f1, fOCO40M, fOCO-F, fOCO-S, fC32, fC)" some description added
8.7.2 "When the CM27 Bit is 1 (Oscillation Stop/Re-oscillation Detect Interrupt)" partially
121
deleted
Table 8.7 "After Main Clock Oscillation Stop/Re-Oscillation Detection When the CM27 Bit is 1"
121
description for bits CM14, CM21, CM22, and CM23 added
122
8.7.3 "Using the Oscillation Stop/Re-Oscillation Detect Function" partially modified
131
9.3 "Clocks" and 9.3.1 "Normal Operating Mode" partially modified
131-132
9.3.1.1 "High-Speed Mode and Medium-Speed Mode" to 9.3.1.7 "Low Power Mode" modified
133
Table 9.2 "Clocks in Normal Operating Mode" note 4 modified
141
9.3.3.4 "Exiting Wait Mode" partially modified
Revision History
C- 17
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