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M16C/5L Group, M16C/56 Group
10.2
Registers
Table 10.2
Registers
Address
0005h
Processor Mode Register 1
0010h
Program 2 Area Control Register
0221h
Flash Memory Control Register 1
10.2.1
Processor Mode Register 1 (PM1)
Processor Mode Register 1
b7
b6 b5 b4
b3
b2
b1
0
0
0
1
0
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.
The PM12 bit becomes 1 by a program. Setting it to 0 has no effect.
PM10 (Data flash enable bit) (b0)
This bit is used to select the function of addresses 0E000h to 0FFFFh.
Data flash includes block A (addresses 0E000h to 0EFFFh) and block B (addresses 0F000h to
0FFFFh). When data flash is selected by the setting of the PM10 bit, both block A and block B can be
used.
The PM10 bit automatically becomes 1 while the FMR01 bit in the FMR0 register is 1 (CPU rewrite
mode).
PM17 (Wait Bit) (b7)
This is a software wait select bit for internal memory.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Register
Symbol
b0
PM1
Bit Symbol
Bit Name
PM10
Data flash enable bit
—
Reserved bit
(b1)
Watchdog timer function select bit
PM12
—
Reserved bit
(b3)
—
Reserved bits
(b6-b4)
PM17
Wait bit
Symbol
PM1
PRG2C
FMR1
Address
0005h
Function
0: Reserved area (0E000h to 0FFFFh )
1: Data flash (0E000h to 0FFFFh)
Set to 0.
0: Watchdog timer interrupt
1: Watchdog timer reset
Set to 1.
Set to 0.
0: No wait state
1: One wait
10. Processor Mode
Reset Value
0000 1000b
XXXX XX00b
00X0 XX0Xb
Reset Value
00001000b
RW
RW
RW
RW
RW
RW
RW
Page 140 of 803
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