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REVISION HISTORY
Rev.
Date
1.00
Jan. 31, 2010
A/D Converter
CRC Calculator
Flash Memory
Electrical Characteristics
M16C/5L Group, M16C/56 Group Hardware Manual
Page
Table 22.9 "Functions by Write Access to the S10 Register" "Selects communication mode"
522
divided into four modes
"PIN (I2C-bus Interface Interrupt Request Bit) (b4)" description added to the third bullet in
524
"Conditions to become 0"
Table 22.11 "CCR4 to CCR0 Bit Settings and Bit Rates (fVIIC = 4 MHz)" "167" in high-speed
528
clock mode and "16.7" in standard clock mode modified to "166" and "16.6" respectively
22.3.2 "Generation of Start Condition" description added to (2); "after the falling edge of the BB
530
bit" in the 14th line modified to "after the BB bit changes from 1 to 0"
Figure 22.10 "Start Condition Overlap Protect Operation" the illustration for bits MST and TRX
534
modified
22.3.5 "Start Condition Overlap Protect" "and the S00 register" added to the second line below
534
Figure 22.10
536
22.3.6 "Arbitration Lost" description for (a) modified; The last paragraph added
542
22.3.9 "Timeout Detection" description for the last bullet deleted
544
22.3.10.2 "Master Transmission" "Check whether ACK presents" deleted from (B)
545
22.3.10.3 "Master Reception" "Check whether ACK presents" deleted from (B)
22.3.10.4 "Slave Reception"
546
(2) deleted from (A); "1 (no ACK presents)" modified to "0 (ACK presents)" in (B); (2) added to
(C)
544
22.3.10.5 "Slave Transmission" "Check whether ACK presents" deleted from (B)
2
Table 22.15 "I
C-bus Interrupt" "Completion of transmitting slave address" deleted from
549
interrupt source
Table 24.1 "A/D Converter Specifications" specification for "Integral nonlinearity error"
622
modified
625
24.2 "Registers" description for the PCR register deleted
24.3.1 "A/D Conversion Cycle" "Divide fAD so φ AD conforms the standard frequency." added;
630
the second paragraph deleted
652
25.1 "Introduction" the last sentence deleted
652
Figure 25.1 "CRC Calculator Block Diagram" modified
653
25.2 "Registers" the order of register diagrams changed
661
"FMR00 (RY/BY status flag) (b0)" two conditions added to "Conditions to become 0"
662
"FMR02 (Lock bit disable select bit) (b2)" the last sentence added
667
"FMR60 (EW1 mode select bit) (b0)" the last sentence added
673
26.8 "CPU Rewrite Mode" the third paragraph for the suspend function added
Table 26.10 "EW0 Mode and EW1 Mode" "Mode after program or erase" modified to "Mode
673
after program/erase, or during program/erase suspend"; "and bits FMR32 and FMR33 in the
FMR3 register" added to the both modes for flash memory status detection
676
Figure 26.4 "Suspend Request" "suspend is requested" modified to "request a suspend"
683
Figure 26.12 "Block Blank Check Command" "command sequence error" detection added
683
26.8.4.8 "Block Blank Check Command" two paragraphs added below Figure 26.12
Table 26.16 "Errors and FMR0 Register States" "block blank check, or read lock bit status"
685
added to error occurrence conditions for command sequence error
686
26.8.5.2 "Handling Procedure for Errors" the seventh line in "Erase error" added
Figure 26.15 "Program Flowchart in EW0 Mode (Suspend Function Enabled)" to Figure 26.17
688-690
"Lock Bit Program Flowchart in EW0 Mode (Suspend Function Enabled)" "Wait td(SR-SUS)"
added
Table 26.18 "Forced Erase Function" "No ID match" added to function for "0 (ROM code
699
protect enabled)"
702
26.9.5 "Standard Serial I/O Mode 2" "The main clock is used" added
Table 26.21 "Pin Functions (Flash Memory Standard Serial I/O Mode 2)" "when the main clock
702
is used" deleted from description for XIN and XOUT
705
26.10.3.10 "Software Command" (e) added
706-761
This chapter revised
J version, Common to 3 V and 5 V
706
Table 27.1 "Absolute Maximum Ratings" "Analog reference voltage" added; Note 1 added
Table 27.2 "Operating Conditions (1)" "High peak output current" and "Low peak output
707
current" added
Revision History
C- 23
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