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M16C/5L Group, M16C/56 Group
18.2.6
Base Timer Control Register 0 (G1BCR0)
Base Timer Control Register 0
b7 b6 b5 b4
b3
b2
b1
0 0 0
Rewrite the G1BCR0 register when the BTS bit in the G1BCR1 register is 0 (base timer reset).
BCK1 and BCK0 (Count source select bit) (b1-b0)
After rewriting bits BCK1 and BCK0 from 00b (clock stopped) to another value, before rewriting these
bits to another value, first set them to 00b, wait four or more cycles of the previous count source, and
then rewrite the bits.
The two-phase pulse clock (10b) can be used only when bits UD1 and UD0 in the G1BCR1 register are
10b (two-phase pulse signal processing). Do not set bits BCK1 and BCK0 to 10b with other count
operations.
When bits BCK1 and BCK0 are 11b and the PCLK0 bit in the PCLKR register is 0, f2TIMS is selected.
When the PCLK0 bit is 1, f1TIMS is selected. Change the PCLK0 bit when bits BCK1 and BCK0 are
00b.
RST4 (Base timer reset source select bit 4) (b2)
When the RST4 bit is 1, set the RST1 bit in the G1BCR1 register to 0.
IT (Base timer interrupt select bit) (b7)
While the IT bit is 0 (overflow of bit 15), when incrementing, if b15 of the base timer becomes 0 from 1
(i.e. the base timer value becomes 0000h from FFFFh) during counting, the base timer overflows.
When decrementing, the base timer overflows if b15 of the base timer becomes 1 from 0 (i.e. 7FFFh
from 8000h).
While the IT bit is 1 (overflow of bit 14), when incrementing, if b14 of the base timer becomes 0 from 1
during counting, the base timer overflows. When decrementing, the base timer overflows if b14 of the
base timer becomes 1 from 0.
When the base timer overflows, the IR bit in the BTIC register becomes 1 (IC/OC base timer interrupt
requested).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
G1BCR0
Bit Symbol
Bit Name
BCK0
Count source select bit
BCK1
Base timer reset source select
RST4
bit 4
—
Reserved
(b5-b3)
CH7INSEL
Channel 7 input select bit
IT
Base timer interrupt select bit
Address
02E2h
Function
b1 b0
0 0: Clock stopped
0 1: Do not set.
1 0: Two-phase pulse clock
1 1: f1TIMS or f2TIMS
0: The base timer is not reset when the base
timer and G1BTRR register values match.
1: The base timer is reset when the base timer
and G1BTRR register values match.
Set to 0.
0: P2_7/OUTC1_7/INPC1_7 pin
1: P1_7/INPC1_7 pin
0: Overflow of bit 15
1: Overflow of bit 14
18. Timer S
Reset Value
00h
RW
RW
RW
RW
RW
RW
RW
Page 357 of 803
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