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REVISION HISTORY
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1.10 Sep. 01, 2011
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M16C/5L, M16C/56 Group User's Manual: Hardware
9.3.1.3 40 MHz On-Chip Oscillator Mode:
Changed the description for the clock division of fOCO-F in the first paragraph.
9.3.1.6 Low-Speed Mode: Changed the division of fOCO-F for when bits CM21 and FRA01 are
both 1.
9.3.1.7 Low Power Mode: Deleted the explanation about the CM06 bit.
Table 9.2 Clocks in Normal Operating Mode:
• Changed "fOCO-F divided by 2, 4, or 8" to "fOCO-F divided by 1".
• Changed "and/or" to "and" for the explanation of bit settings in note 1.
• Combined notes 2 to 6 into note 2.
Table 9.3 Clock-Related Bit Setting and Modes, Table 9.4 Selecting Clock Division Related Bits,
Table 9.5 Example Settings for 40 MHz On-Chip Oscillator Mode Division Related Bits:
Added a legend below each table.
9.3.2 Clock Mode Transition Procedure:
• (1) in b: Changed "Select the reference clock division" to "Select the division of reference
frequency counter".
• e: Added "low-speed mode".
• i: Corrected "40 kHz on-chip oscillator" typo to "40 MHz on-chip oscillator".
9.3.3 Wait Mode: Changed the explanation about the operation of peripheral functions.
9.3.3.2 Entering Wait Mode: Added a procedure for entering wait mode.
9.3.3.4 Exiting Wait Mode: Deleted the explanations below the table except the explanation about
exiting wait mode using an interrupt.
Table 9.7 Resets and Interrupts to Exit Wait Mode and Conditions for Use:
• Changed the conditions for use in the Serial interface row.
• Changed the conditions for use in the CM02 = 1 column of the A/D converter row.
• Changed the conditions for use in the Voltage monitor 2 row.
• Changed "Usable when fOCO-S is supplied" to "Usable" in the Voltage monitor 0 reset row.
• Changed the conditions for use in the Voltage monitor 2 reset row.
9.3.4.1 Entering Stop Mode:
• Deleted "However, when the PM21 bit in the PM2 register is 1 (disables a clock change) or when
the CSPRO bit in the CSPR register is 1 (watchdog timer count source protect mode enabled),
writing the CM10 bit has no effect and the MCU does not enter stop mode." from the first
paragraph.
• Moved some of explanations under Table 9.9 here and added a procedure for entering stop
mode.
Table 9.10 CPU Clock After Exiting Stop Mode:
• Changed the description for the fOCO-F clock division.
• Deleted note 1.
9.4 "Power Control in Flash Memory": Added title.
Figure 9.2 Stop and Restart of the Flash Memory:
• Deleted the description of "Program A".
• Changed the ranges of the Stop Procedure and Restart Procedure.
• Added "or 40 MHz on-chip oscillator to start oscillator" in the first process box in the restart
procedure.
• Deleted note 4.
9.4.2.1 Slow Read Mode:
• Changed "f(BCLK) must be f(SLOW_R)" to "f(BCLK) is less than or equal to f(SLOW_R)" in the
first line.
• Added an explanation for when no wait operation is required.
Figure 9.3 Setting and Canceling Slow Read Mode, Figure 9.4 Setting and Canceling Low Current
Consumption Read Mode:
Deleted the last process to restore the CPU clock from the canceling procedure.
9.4.2.2 Low Current Consumption Read Mode:
Deleted "To enter low current consumption read mode, set or the sub clock or fOCO-S divided by 8
or 16 as the CPU clock." from the first paragraph.
9.5.2 A/D Converter: Deleted the explanation for when A/D conversion is performed.
9.6.1 CPU Clock: Added line 2.
Description
Summary
C- 4
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