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M16C/5L Group, M16C/56 Group
21.5.3.3
Setup and Hold Times When Generating a Start/Stop Condition
When generating a start condition, the hold time (t
generating a stop condition, the setup time (t
When the SDA digital delay function is enabled, take delay time into consideration (see 21.3.3.7
"SDA Digital Delay").
The following shows a calculation example of hold and setup times when generating a start/stop
condition.
Calculation example when setting 100 kbps
•
U2BRG count source: f1 = 20 MHz
•
U2BRG register setting value: n = 100 - 1
•
SDA digital delay setting value: DL2 to DL0 are 101b (5 or 6 cycles of U2BRG count source)
(theoretical value) = f1 / (2(n+1)) = 20 MHz / (2 × (99 + 1)) = 100 kbps
f
SCL
= delay cycle count / f1 = 6 / 20 MHz = 0.3 μ s
t
DL
t
(theoretical value) = 1 / (2f
HD:STA
t
(theoretical value) = 1 / (2f
SU:STO
f
(actual value) = t
HD:STA
f
(actual value) = t
SU:STO
Internal clock
(U2BRG output)
SCL
SDA
f
: SCL clock
SCL
t
: SDA digital delay time
DL
t
: Hold time when generating a start condition
HD:STA
t
: Set-up time when generating a stop condition
SU:STO
Figure 21.34 Setup and Hold Times When Generating Start and Stop Conditions
21.5.3.4
Restrictions on the Bit Rate When Using the U2BRG Count Source
2
In I
C mode, set the U2BRG register to a value of 03h or greater.
A maximum of three U2BRG count source cycles are necessary until the internal circuit
acknowledges the SCL clock level. The connectable I
U2BRG count source speed. If a value between 00h to 02h is set to the U2BRG register, bit slippage
may occur.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
(theoretical value)) = 1 / (2 × 100 kbps) = 5 μ s
SCL
(theoretical value)) = 1 / (2 × 100 kbps) = 5 μ s
SCL
(theoretical value) - t
HD:STA
(theoretical value) + t
SU:STO
1 / f
(theoretical value)
SCL
1 / (2f
(theoretical value))
SCL
t
HD:STA
(theoretical value)
t
HD:STA
(actual value)
t
DL
21. Serial Interface UARTi (i = 0 to 4)
:STA) is a half cycle of the SCL clock. When
HD
:STO) is a half cycle of the SCL clock.
SU
= 5 μ s - 0.3 μ s = 4.7 μ s
DL
= 5 μ s + 0.3 μ s = 5.3 μ s
DL
1 / (2f
2
C-bus bit rate is one-third or less than the
(theoretical value))
SCL
t
SU:STO
(theoretical value)
t
SU:STO
(actual value)
t
DL
Page 497 of 803
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