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M16C/5L Group, M16C/56 Group
28.7
Notes on Programmable I/O Ports
Note
The 64-pin package has no P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P9_5 to P9_7.
28.7.1
Pin Assignment Control
Bits PACR2 to PACR0 in the PACR register are 000b after reset. Set 010b (64-pin package) or 011b
(80-pin package) to select the pin package, depending on the product.
After setting bits PACR2 to PACR0, set the programmable I/O ports and I/O pins for peripherals.
Influence of SD
28.7.2
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V/RXD1, P7_3/ CTS2 / RTS2 /TA1IN/ V /TXD1, P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/U/TSUDA, P8_1/TA4IN/ U /TSUDB
28.7.3
Input Voltage Threshold
The input threshold voltage differs in the programmable I/O port and peripherals. When the
programmable I/O port and peripheral is sharing the same pin, and the pin input level is lower than VIH
and higher than VIL (input voltage is neither high or low), the input signal voltage level may be
determined differently between the programmable I/O port and peripheral because the input voltage
thresholds for those two are not necessarily the same.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
28. Usage Notes
Page 769 of 803
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