Renesas M16C/50 Series User Manual page 412

M16C/5L Group, M16C/56 Group
RST2 bit in the G1BCR1 register
The above assumes the following:
Bits UD1 and UD0 in the G1BCR1 register are 00b (increment).
Notes:
1. The INT1 pin should be driven low for at least 1.5 fBT1 cycles.
2. An IC/OC base timer interrupt request is not generated by base timer reset with the INT1 pin. An INT1 interrupt request is
generated according to the settings of the INT1IC register and the IFSR1 bit in the IFSR register.
Figure 18.10 Base Timer Reset with INT1 Pin Input
Table 18.7 to Table 18.9 list the relationship between base timer count operation and the count value
when the base timer is reset.
Table 18.7 Increment
Reset Source
RST1 reset
RST2 reset
RST4 reset
Table 18.8 Increment/Decrement
Reset Source
RST1 reset
RST2 reset
RST4 reset
Table 18.9 Two-Phase Pulse Signal Processing
Reset Source
RST1 reset
RST2 reset
RST4 reset
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Base timer m - 2
INT1
Count Direction
No change (increments)
No change (increments)
No change (increments)
Increment Operation
Count direction
Increment to
decrement
Increment to
decrement
Increment to
decrement
Increment Operation
Count direction Count value
No change
(increments)
No change
(increments)
No change
(increments)
m - 1 m
(Note 1)
Count value Count direction
—
(decrements)
(count continues)
—
(decrements)
(count continues)
—
(decrements)
(count continues)
Count direction
No change
0000h
(decrements)
No change
0000h
(decrements)
No change
0000h
(decrements)
m + 1 0000h 0001h
Count Value
0000h
0000h
0000h
Decrement Operation
Count value
No change
(count continues)
No change
(count continues)
No change
(count continues)
Decrement Operation
Count value
(count continues)
0000h
(count continues)
18. Timer S
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—
—
—
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