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M16C/5L Group, M16C/56 Group
21.2.9
UART2 Special Mode Register 4 (U2SMR4)
UART2 Special Mode Register 4
b7 b6 b5 b4
b3
b2
b1
STAREQ (Start condition generate bit) (b0)
The STAREQ bit becomes 0 when a start condition is generated.
This bit is used in master mode of I
2
register to 1 (I
C mode). Do not set this bit to 1 when the IICM bit is 0.
RSTAREQ (Restart condition generate bit) (b1)
The RSTAREQ bit becomes 0 when a restart condition is generated.
This bit is used in master mode of I
2
register to 1 (I
C mode). Do not set this bit to 1 when the IICM bit is 0.
STPREQ (Stop condition generate bit) (b2)
The STPREQ bit becomes 0 when a stop condition is generated.
This bit is used in master mode of I
2
register to 1 (I
C mode). Do not set this bit to 1 when the IICM bit is 0.
STSPSEL (SCL, SDA output select bit) (b3)
This bit is used in master mode of I
2
register to 1 (I
C mode). Do not set this bit to 1 when the IICM bit is 0.
Set the STSPSEL bit to 1 (select start condition/stop condition generate circuit) after setting the
STARREQ, RSTAREQ, or STPREQ bit to 1 (start).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
U2SMR4
Bit Symbol
Bit Name
STAREQ
Start condition generate bit
Restart condition generate
RSTAREQ
bit
STPREQ
Stop condition generate bit
STSPSEL
SCL, SDA output select bit
ACKD
ACK data bit
ACKC
ACK data output enable bit
SCLHI
SCL output stop bit
SWC9
SCL wait auto insert bit 3
2
C mode. To set this bit to 1, preset the IICM bit in the U2SMR
2
C mode. To set this bit to 1, preset the IICM bit in the U2SMR
2
C mode. To set this bit to 1, preset the IICM bit in the U2SMR
2
C mode. To set this bit to 1, preset the IICM bit in the U2SMR
21. Serial Interface UARTi (i = 0 to 4)
Address
0264h
Function
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Select serial I/O circuit
1 : Select start condition/stop condition
generate circuit
0 : ACK
1 : NACK
0 : Serial data output
1 : ACK data output
If stop condition is detected,
0 : Do not stop SCL2 output
1 : Stop SCL2 output
0 : No wait-state/wait-state cleared
1 : Hold the SCL2 pin low after the ninth bit
of the SCL2 is received
Reset Value
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
Page 444 of 803
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