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M16C/5L Group, M16C/56 Group
18.5.3
Changing Registers ICOCiIC (i = 0, 1)
While the G1IEij bit in the G1IEi register is 1 (IC/OC interrupt 1 request enabled), use the AND, OR,
BCLR, or BSET instruction to change bits ILVL2 to ILVL0 in the ICOCiIC register at the point where a
channel j interrupt request may be generated (j = 0 to 7). The IR bit becomes 1 (interrupt requested) if a
channel j interrupt is generated while executing these instructions.
If the MOV instruction is used to perform the above, when a channel j interrupt request is generated
while executing the MOV instruction, the IR bit does not become 1, and the interrupt request is ignored.
The G1IRj bit in the G1IR register becomes 1 (interrupt requested) at this timing. If the G1IRj remains 1,
subsequent IC/OC interrupt i requests are not generated.
When timer S is initialized, change registers ICOCiIC after registers ICOCiIC and G1IR are both set to
00h.
18.5.4
Output Waveform During the Base Timer Reset with the BTS bit
When the BTS bit in the G1BCR1 register is set to 0 (base timer reset), the waveform output pin level
remains as it is at that point. This output level is held until the base timer value matches the G1POj
register value after the BTS bit is set to 1 (base timer starts counting).
18.5.5
OUTC1_0 Pin Output During the Base Timer Reset with the G1PO0 register
While the RST1 bit in the G1BCR1 register is set to 1 (the base timer is reset when the base timer
matches the G1PO0 register), when the base timer matches the G1PO0 register, the base timer is
reset after two fBT1 cycles. During the two fBT1 cycles from when the base timer value matches the
G1PO0 register value to the base timer being reset, the OUTC1_0 pin is driven high. Thus set the
EOC0 bit in the G1OER register to 1 (output disabled).
18.5.6
Interrupt Request When Selecting Time Measurement Function
When the FSCj bit (j = 0 to 7) in the G1FS register is set to 1, and the IFEj bit in the G1FE register is
also set to 1, the G1IRj bit in the G1IR register, or the IR bits in registers ICOCiIC (i = 0, 1) or ICOCHjIC
(j = 0 to 3) may become 1 (interrupt requested) after a maximum of two fBT1 cycles.
When using IC/OC interrupt i or IC/OC channel j interrupt, set bits FSCj and IFEj to 1, then perform the
following:
(1) Wait for two or more fBT1 cycles.
(2) Set the IR bit in the ICOCiIC register and/or the ICOCHjIC register to 0.
(3) Wait for three or more fBT1 cycles after the time measurement function is selected. Set the G1IR
register to 00h after setting the IR bit in the ICOCiIC register to 0.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
18. Timer S
Page 397 of 803
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