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M16C/5L Group, M16C/56 Group
Table 18.13
Registers and Settings in Single-Phase Waveform Output Mode
Register
G1POj
G1FS
G1FE
MOD1 and MOD0 Set to 00b.
G1POCRj
G1OER
G1IOR0
IOj1 and IOj0
G1IOR1
G1BCR1
UD1 and UD0
j = 0 to 7, however, when the RST1 bit in the G1BCR1 register is 1 (the base timer is reset when the base
timer and G1PO0 register values match), then j = 1 to 7.
Notes:
1.
This table does not describe a procedure.
2.
When the INV bit in the G1POCRj register is 0 (output level not inverted).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bit
—
Set the timing for an output level to become high.
FSCj
Set to 0 (waveform generation function selected).
IFEj
Set to 1 (channel j function enabled).
IVL
Select a default value of an output level.
RLD
Select the reload timing for the G1POj register value.
INV
Select whether an output level is inverted.
EOCj
Set to 1 when the OUTC1_j output is disabled.
Select an output level when compare results match.
Set to 00b.
(1)
Function
(2)
18. Timer S
Page 382 of 803
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