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M16C/5L Group, M16C/56 Group
9.6
Notes on Power Control
9.6.1
CPU Clock
When switching the CPU clock source, wait until oscillation of the switched clock source is stable.
After exiting stop mode, wait until oscillation stabilizes before changing the division.
9.6.2
Wait Mode
•
Insert four or more NOP instructions following the WAIT instruction. When entering wait mode,
because the instruction queue prefetches instructions that follow the WAIT instruction, prefetched
instructions are sometimes executed prior to the interrupt routine used to exit wait mode. As shown
below, when the instruction to set the I flag to 1 is allocated just before the WAIT instruction,
interrupt requests are not accepted before the WAIT instruction is executed.
The following is an example program for entering wait mode:
Program Example: FSET
•
Do not enter wait mode from PLL operating mode. To enter wait mode from PLL operating mode,
first enter medium-speed mode, then set the PLC07 bit to 0 (PLL off).
•
Do not enter wait mode from low current consumption read mode. To enter wait mode from low
current consumption read mode, set the FMR23 bit in the FMR2 register to 0 (low current
consumption read mode disabled).
•
Do not enter wait mode from CPU rewrite mode. To enter wait mode from CPU rewrite mode, first
set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled), then disable the DMA
transfer.
•
Set the PLC07 bit in the PLC0 register to 0 (PLL off). When the PLC07 bit is 1 (PLL on), current
consumption cannot be reduced even in wait mode.
9.6.3
Stop Mode
When exiting stop mode by a hardware reset, drive the RESET pin low for 20 fOCO-S cycles or
•
more.
•
Set the MR0 bit in the TAiMR register (i = 0 to 4) to 0 (pulse not output) when using timer A to exit
stop mode.
•
When entering stop mode, insert a JMP.B instruction immediately after executing an instruction
that sets the CM10 bit in the CM1 register to 1 (stop mode), and then insert at least four NOP
instructions. When entering stop mode, the instruction queue reads ahead the instructions
following the instruction which sets the CM10 bit to 1. Thus, some of the instructions may be
executed before the MCU enters stop mode or before the interrupt routine for returning from stop
mode. As shown below, when the instruction to set the I flag to 1 is allocated just before the
instruction to set the CM10 bit to 1, interrupt requests are not accepted before entering stop mode.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
I
;
WAIT
; Enter wait mode
NOP
; Insert at least four NOP instructions
NOP
NOP
NOP
9. Power Control
Page 137 of 803
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