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REVISION HISTORY
Rev.
Date
1.00
Jan. 31, 2010
Special Function Registers (SFRs)
Resets
Voltage Detector
Clock Generator
Power Control
Processor Mode
Programmable I/O Ports
Interrupts
179, 180
M16C/5L Group, M16C/56 Group Hardware Manual
Page
15
Table 1.10 "Pin Names, 64-Pin Package (2/2)" TB2IN moved from 63 pin to 64 pin
Table 1.11 "Pin Functions (64-Pin and 80-Pin Packages)" "Three-phase motor control timer
16
output" modified to "Three-phase motor control timer"; Note 1 added
24
Table 4.2 SFR List (2) "the VW2C3 bit" in note 2 modified to "bits VW2C2 and VW2C3"
Table 4.35 "Registers with Write-Only Bits" the order of registers changed; "CAN0 Receive
57
FIFO Pointer Control Register" and "CAN0 Transmit FIFO pointer Control Register" added
61
Figure 6.1 "Reset Circuit Block Diagram" illustration for the VD2LS register added
Table 7.2 "Register List" notes 4 and 6 added; "the VW2C3 bit" in note 7 modified to "Bits
74
VW2C2 and VW2C3"
7.2.3 "Voltage Monitor Function Select Register (VWCE)" typo corrected from "PCR3" to
77
"PRC3"
7.2.4 "Voltage Detector 2 Level Select Register (VD2LS)" RW for b7 to b4 modified to RW;
78
Function for VD2LS0 to VD2LS3 modified; typo corrected from "PCR3" to "PRC3"
7.2.6 "Voltage Monitor 2 Control Register (VW2C)" "The VW2C3 bit" in the 4th line modified to
80
"Bits VW2C2 and VW2C3"
82
7.3 "Optional Function Select Area" description for "programmed products" added
7.3.1 "Option Function Select Address 1 (OFS1)" three lines below the register diagram
82
deleted
82
"LVDAS (Voltage Detector 0 Start Bit) (b6)" added
83
7.4.1 "Digital Filter" "next sampling timing" modified to "third sampling timing" in the sixth line
90
8.1 "Introduction" description for the fifth bullet deleted
Table 8.1 "Clock Generator Specifications" and Figure 8.1 "System Clock Generator"
91, 92
description for "Dedicated 125-kHz on-chip oscillator for watchdog timer" deleted (moved to
13. "Watchdog Timer")
"CM01-CM00 (Clock Output Function Select Bit) (b1-b0)" "the CM01 and CM00 bit settings
95
enabled" in the second line modified to "selected by the CM01 and CM00 bit"
96
"CM06 (Main Clock Division Select Bit) (b6)" description of the second bullet deleted
98
"CM15 (XIN-XOUT Drive Level Select Bit) (b5)" description modified
101
8.2.5 "Peripheral Clock Select Register (PCLKR)" Bit Name for PCLK0 corrected
8.2.7 "Processor Mode Register 2 (PM2)" description of "Once the PM21 bit is set to 1, it can-
103
not be set to 0 by a program (writing a 0 has no effect)." added
8.3.5 "125-kHz On-Chip Oscillator Clock (fOCO-S)"
typo in the description for "To stop fOCO-S oscillation" corrected from "CM14 bit becomes 1
109
(125 kHz on-chip oscillator oscillates)" to "CM14 bit becomes 0 (125 kHz on-chip oscillator
oscillates)"
"FMR01 (CPU Rewrite Mode Select Bit) (b1)" "FMSTP (Flash Memory Stop Bit) (b3)"
122
"located in an area other than the flash memory" modified to "in the RAM"
"FMR23 (Low-Current Consumption Read Mode Enable Bit) (b3)" the second paragraph
124
modified
Table 9.7 "Resets and Interrupts to Exit Wait Mode and Usage Conditions" usage conditions
133
for "Multi-master I
138
9.4 "Stopping Flash Memory" "an area other than the flash memory" modified to "the RAM"
10.3 "Software Wait" note 1 deleted (moved to 27.1.4 and 27.4.4 "Flash Memory Electrical
148
Characteristics")
11.2 "I/O Ports and Pins" diagrams for I/O ports revised; Table 11.3 "I/O Ports (Basic)" to Table
150
11.8 "I/O Ports (XC)" added
162-163
11.3.7 to 11.3.9 "Input Threshold Select Register 0/1/2" description for the input level added
169
11.4.2 "Priority Level of Peripheral Function I/O" added
"IR (Interrupt Request Bit) (b3)" description modified to "Do not write 1 when the IR bit is 0"
183
12.2.6 "Interrupt Source Select Register (IFSR)" function for IFSR6 and IFSR7 modified
206
12.13.2 "SP Setting" the second paragraph added
Revision History
2
C bus" and "Voltage monitor 0 reset" modified
C- 21
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