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REVISION HISTORY
Rev.
Date
Page
1.10 Sep. 01, 2011 Memory
23
Special Function Registers (SFRs)
55
56
Resets
60
60
61
62
63
64
66
67
68
69
69
70
70
71
72
Voltage Detector
88
Clock Generator
Chap. 8.
Chap. 8. Deleted descriptions regarding 0004h Processor Mode Register 0.
90
91
93
M16C/5L, M16C/56 Group User's Manual: Hardware
Figure 3.1 Memory Map:
• Added note 2.
• Added footnote reference numbers (1) and (2).
4.2.1 Register Settings: Added the description regarding read-modify-write instructions.
Table 4.33 Read-Modify-Write Instructions: Added.
Table 6.1 Types of Resets: Added the "Registers and Bits Not to Reset" column.
Figure 6.1 Reset Circuit Block Diagram: Deleted SFR names from the figure, and the SFR details
are described in Table 6.2 Classification of SFRs Which are Reset.
Table 6.2 Classification of SFRs Which are Reset: Added.
Table 6.4 Registers:
• Changed the reset value of the RSTFR register from "XX0X 001Xb".
• Added note 1.
6.2.2 Reset Source Determine Register (RSTFR):
HWR bit explanation: Changed "the reset" to "the hardware reset" in the last sentence.
OSDR bit explanation: Added "Conditions to become 0" to the explanation.
6.3.1 Optional Function Select Address 1 (OFS1): Added "This bit is enabled in single-chip mode,
while disabled in boot mode." to the LVDAS bit explanation.
Table 6.7 Pin Status When RESET Pin Level is Low: Changed note 1.
Figure 6.3 Reset Sequence: Changed the oscillation period of XIN.
6.4.2 Hardware Reset:
Changed "20 fOCO-S cycles" to "tw(RSTL)" in When the power supply is stable, (2).
Changed "20 fOCO-S cycles" to "1/fOCO-S x 20 cycles" in When the power is turned on, (4).
6.4.3 Power-On Reset Function: Changed "at 0.8 VCC or more" to "in the range of VIH" in the first
paragraph.
Figure 6.5 Example of Power-On Reset Operation: Changed "External power VCC" to "VCC".
6.4.6 Oscillator Stop Detect Reset: Added "after oscillator stop detect reset" to the sentence
starting with "The OSDR bit...".
6.4.7 Watchdog Timer Reset: Added "after watchdog timer reset" to the sentence starting with "The
WDR bit...".
6.4.8 Software Reset: Added "after software reset" to the sentence starting with "The SWR bit...".
Figure 6.6 SVCC Timing: Revised.
Figure 7.6 Voltage Monitor 2 Interrupt/Reset Operation Example: Added "or above" to note 1.
Changed the bit name from "XCIN-XCOUT drive level select bit" to "XCIN-XCOUT drive capacity
select bit".
Table 8.1 Clock Generator Specifications:
• Changed the description for the Clock frequency row.
• Rewrote note 1.
Figure 8.1 System Clock Generator:
• Deleted buffers in the peripheral clock, and added the main clock.
• Changed the description of the circuit after the main clock in the Oscillator Stop/Restart Detector.
• Changed a part of the configuration in the PLL frequency synthesizer.
8.2.1 System Clock Control Register 0 (CM0):
• Deleted I/O port names from the Function column in the register diagram.
• Rewrote bit explanations.
• Added description for 40 MHz on-chip oscillator mode to the CM05 bit explanation.
Description
Summary
C- 2
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