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21.4
Interrupts................................................................................................................................... 493
21.4.1
Interrupt Related Registers .............................................................................................. 493
21.4.2
Reception Interrupt .......................................................................................................... 494
21.5
Notes on Serial Interface UARTi (i = 0 to 4) ............................................................................. 495
21.5.1
Common Notes on Multiple Modes ................................................................................. 495
21.5.2
Clock Synchronous Serial I/O Mode ................................................................................ 495
21.5.3
Special Mode 1 (I
21.5.4
Special Mode 4 (SIM Mode) ............................................................................................ 498
22. Multi-master I
22.1
Introduction ............................................................................................................................... 499
22.2
Registers Descriptions.............................................................................................................. 502
22.2.1
I2C0 Data Shift Register (S00) ........................................................................................ 503
22.2.2
I2C0 Address Register i (S0Di) (i = 0 to 2) ...................................................................... 504
22.2.3
I2C0 Control Register 0 (S1D0) ....................................................................................... 505
22.2.4
I2C0 Clock Control Register (S20) .................................................................................. 507
22.2.5
I2C0 Start/Stop Condition Control Register (S2D0) ......................................................... 509
22.2.6
I2C0 Control Register 1 (S3D0) ....................................................................................... 510
22.2.7
I2C0 Control Register 2 (S4D0) ....................................................................................... 514
22.2.8
I2C0 Status Register 0 (S10) ........................................................................................... 516
22.2.9
I2C0 Status Register 1 (S11) ........................................................................................... 521
22.3
Operations ................................................................................................................................ 522
22.3.1
Clock ................................................................................................................................ 522
22.3.2
Generating a Start Condition ........................................................................................... 525
22.3.3
Generating a Stop Condition ........................................................................................... 527
22.3.4
Generating a Restart Condition ....................................................................................... 528
22.3.5
Start Condition Overlap Protect ....................................................................................... 529
22.3.6
Arbitration Lost ................................................................................................................ 531
22.3.7
Detecting Start/Stop Conditions ....................................................................................... 533
22.3.8
Operation after Transmitting/Receiving a Slave Address or Data ................................... 535
22.3.9
Timeout Detection ........................................................................................................... 536
22.3.10
Data Transmit/Receive Examples ................................................................................... 537
22.4
Interrupts................................................................................................................................... 542
22.5
Notes on Multi-master I
22.5.1
Limitation on CPU Clock .................................................................................................. 545
22.5.2
Register Access ............................................................................................................... 545
23. CAN Module ........................................................................................ 546
23.1
CAN SFRs ................................................................................................................................ 549
23.1.1
CAN0 Control Register (C0CTLR) .................................................................................. 550
23.1.2
CAN0 Clock Select Register (C0CLKR) ......................................................................... 554
2
C Mode) ............................................................................................. 496
2
C-bus Interface ............................................................. 499
2
C-bus Interface .................................................................................. 545
A- 12
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