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M16C/5L Group, M16C/56 Group
Table 15.15
Registers and Settings in PWM Mode
Register
PCLKR
CPSRF
TCKDIVC0
PWMFS
TACS0 to TACS2
TAPOFS
TAOW
TAi1
TABSR
ONSF
TRGSR
UDF
TAi
TAiMR
i = 0 to 4
Note:
1.
This table does not describe a procedure.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bit
PCLK0
Select the count source.
CPSR
Write 1 to reset the clock prescaler.
TCDIV00
Select the clock used prior to dividing timer AB frequency.
PWMFSi
Set to 0.
7 to 0
Select the count source.
POFSi
Select the output polarity.
TAiOW
Set to 0.
15 to 0
- (setting unnecessary)
Set to 1 when starting counting.
TAiS
Set to 0 when stopping counting.
TAiOS
Set to 0.
TAZIE
Set to 0.
TA0TGH to TA0GL Select a count trigger.
TAiTGH to TAiTGL Select a count trigger.
TAiUD
Set to 0.
TAiP
Set to 0.
15 to 0
Select the PWM pulse width and cycles.
7 to 0
Refer to the TAiMR register below.
(1)
Setting
15. Timer A
Page 266 of 803
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