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REVISION HISTORY
Rev.
Date
Page
1.10 Sep. 01, 2011
137
137
138
138
Processor Mode
143
Programmable I/O Ports
161
166
Interrupt
170
171, 172
174
181
182
184
186
192
Watchdog Timer
199
202
203
206
207
DMAC
212
M16C/5L, M16C/56 Group User's Manual: Hardware
9.6.2 Wait Mode:
• Added lines 4 and 5 to the first bullet.
• Deleted second bullet in the previous version and added the second to fifth bullets.
9.6.3 Stop Mode:
• Added the last sentence to the third bullet.
• Deleted fifth bullet in the previous version and added fourth to ninth bullets.
9.6.4 Low Current Consumption Read Mode: Added the third bullet.
9.6.5 Slow Read Mode: Added.
10.4 Bus Hold: Added.
11.3.12 Port Pi Direction Register (PDi) (i = 0 to 3, 6 to 10):
Port P9 Direction Register: Corrected typo in all bit symbols from "P9_" to "PD9_".
11.6.2 Influence of SD :
• Changed the title from "Effect of SD Pin".
• Changed the explanation.
12.2.1 Processor Mode Register 2 (PM2): Changed the bit name and the function of the PM25 bit.
12.2.2 Interrupt Control Register 1 and 12.2.3 Interrupt Control Register 2: Moved symbol and
address information to the tables below the register diagram.
12.2.5 Interrupt Source Select Register 2 (IFSR2A):
Changed the Function column of the IFSR24 bit.
12.5.1.3 Watchdog Timer Interrupt:
Changed "initialize the watchdog timer" to "refresh the watchdog timer".
12.6.1 Fixed Vector Tables: Changed "used by the ID code check function" to "used for the ID code
check function and OFS1 address".
Table 12.7 Relocatable Vector Tables (2/2): Changed note 5.
Figure 12.3 Time Required for Executing Interrupt Sequence: Changed "accept instructions" to
"prefetch" in note 1.
12.10 Key Input Interrupt: Rewritten.
Table 13.1 Watchdog Timer Specifications:
• Changed "Watchdog timer counter reset value conditions" to "Watchdog timer counter refresh
timing" in the Item column.
• Changed the description for Prescaler divide ratio in the Selectable functions row.
13.2.1 Voltage Monitor 2 Control Register (VW2C):
• Changed the VW2C3 bit name from "WDT detection flag" to "Watchdog timer detection flag".
• Changed the VW2C6 bit name from "Voltage monitor 2 circuit mode select bit" to "Voltage
monitor 2 mode select bit".
• Deleted "voltage monitor 1 reset" from the register explanation.
• VW2C3 bit explanation: Deleted the first bullet from the description for Conditions to become 0.
13.2.2 Count Source Protection Mode Register (CSPR):
• Changed bits b6 to b0 from "Reserved bits" to "No register bits".
• Changed "125-kHz on-chip oscillator" to "Dedicated 125 kHz on-chip oscillator" in the first bullet
of the CSPRO bit explanation.
13.3.2 Optional Function Select Address 2 (OFS2): Changed the bit name of WDTUFS1 and
WDTUFS0 from "Watchdog timer reset value setting bit" to "Watchdog timer initial setting bit".
13.4.1 Refresh Operation Period: Rewritten.
Table 14.1 DMAC Specifications:
• Corrected "DMAiCON" typo to "DMiCON" in the Specifications column of DMA transfer start.
• Changed "SARi or DARi pointer" to "SARi or DARi register" in the Specifications column of the
Reload timing for forward address pointer and DMAi transfer counter row.
Description
Summary
C- 5
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