Page 1 REU11B0001-0100Z M30240 Group User’s Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.00 Revision date: Sep. 24, 2003 www.renesas.com...
Page 2 The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
Page 3 Preface This user’s manual describes the function and features of Renesas’s M30240 16-bit microcontroller. The software features are explained to help designers take full advantage of the M16C functions. For details about the software, please refer to the “M16C/60 development series software manual”, and for the develop-...
Page 4 This manual is comprised of six chapters. Use the suggested chapters as a reference for the following topics: Chapter 1: Hardware Understanding hardware specifications Chapter 2: Peripheral Functions Usage Understanding how to use peripheral features and operation timing Chapter 3: Universal Serial Bus UnderstandingUSB applications Chapter 4: Interrupts Understanding interrrupt timing...
Page 5 How to use this Manual This user’s manual is written for the M30240 Group. The user is expected to have the basic knowledge of electric and logic circuits and microcomputers. This manual is used for the products listed in the table below. These products have similar features except for the memories, which differ from one product to another.
Page 6 M16C Family-related document list Usages (Microcomputer development flow) Type of document Contents Selection of microcomputer Data sheet and Hardware specifications (pin assignment, data book memory map, specifications of peripheral func- tions, electrical characteristics, timing charts) Outline design of system User’s manual Detailed description about hardware specifica- tions, operation, and application examples (connection with peripherals, relationship with...
Page 7: Table Of Contents
Table of Contents CHAPTER 1: HARDWARE Description ............2 Features .
Page 8 Timer mode ..............69 Event counter mode .
Page 9 Accessing USB IN/OUT Control and Status Registers ....... . . 137 USB Consecutive Set Address .
Page 10 Repeat-sweep mode 1 ............243 Precautions .
Page 11 USB Related Registers ........... . 294 USB Control Register .
Page 12 Saving Registers ............. . 340 Interrupt Response Time .
Page 13 Special Function Register Quick Access Select the figure number to view the special function registers. Address Register name Acronym Value after reset Figure number 0000 0001 0002 0003 0004 Processor mode register 0 Figure 1.7 0005 Processor mode register 1 Figure 1.7 0006 System clock control register 0...
Page 14 Address Register name Acronym Value after reset Figure number 0038 DMA1 transfer counter TCR1 Figure 1.56 0039 003A 003B 003C DMA1 control register DM1CON 0 0 0 0 0 ? 0 0 Figure 1.55 003D 003E 003F 0040 0041 0042 0043 0044 USB Suspend interrupt control register...
Page 15 Address Register name Acronym Value after reset Figure number 0315 USB Endpoint 0 OUT write count EP0WC Figure 1.46 0316 USB reserved 0317 USB reserved 0318 USB reserved 0319 USB Endpoint 1 IN control/status register EP1ICS Figure 1.47 031A USB Endpoint 1 OUT control/status register EP1OCS Figure 1.48 031B...
Page 16 Address Register name Acronym Value after reset Figure number 0353 0354 0355 0356 0357 0358 0359 035A 035B 035C 035D 035E 035F 0370 0371 0372 0373 0374 0375 0376 0377 Reserved 0378 UART2 transmit / receive mode register U2MR Figure 1.77 0379 UART2 bit rate generator U2BRG...
Page 17 Address Register name Acronym Value after reset Figure number Figure 1.63 Timer A3 mode register Figure 1.66 0399 TA3MR Figure 1.65 Figure 1.68 Figure 1.63 Timer A4 mode register Figure 1.65 039A TA4MR Figure 1.66 Figure 1.68 039B Timer B0 mode register TB0MR 0 0 ? 0 0 0 0...
Page 18 Address Register name Acronym Value after reset Figure number 03D2 03D3 03D4 A-D control register 2 ADCON2 Figure 1.98 03D5 03D6 A-D control register 0 ADCON0 0 0 0 0 0 ? ? ? Figure 1.97 03D7 A-D control register 1 ADCON1 Figure 1.97 03D8...
Page 19: Chapter 1: Hardware
Chapter 1 Hardware...
Page 20: Description
Features M30240 Group 1.1 Description The M30240 group is a 16-bit microcomputer based on the M16C family core technology. They are single-chip USB peripheral microcontrollers based on the Universal Serial Bus (USB) Version 1.1 specification. They are packaged in an 80-pin, molded plastic QFP. These single-chip microcontrollers operate using sophisticated instructions featuring a high level of instruction efficiency, making them capable of executing instructions at high speed.
Page 21: Pin Configuration
Pin Configuration M30240 Group 1.1.3 Pin Configuration Figure 1.1 shows the pin configuration (top view). P03/KI3 P02/KI2 P01/KI1 P00/KI0 P107/AN7 P106/AN6 P37/CLK P105/AN5 P60/CTS0/RTS0 M30240Mx/EC P104/AN4 P61/CLK0 P103/AN3 P62/RxD0 P102/AN2 P63/TxD0 P101/AN1 P64/ CTS1/RTS1/CLKS1 P100/AN0 P65/CLK1 AVss P66/RxD1 P67/TxD1 P70/TxD2/TA0OUT AVcc P71/RxD2/TA0IN Figure 1.1:...
Page 22: Block Diagram
Port P8 Port P10 , P8 Internal peripheral functions Memory System clock generator Timer M16C series 16-bit CPU core Timer TA0 (16 bits) A-D converter Registers Program counter Timer TA1 (16 bits) 10 bits x 8 channels Timer TA2 (16 bits)
Page 23: Performance Outline
Performance outline M30240 Group 1.1.5 Performance outline Table 1.1 is a performance outline of the M30240 group. Table 1.1: Performance outline of M30240 group Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 83ns (f(X ) =12MHz) Memory capacity (See Table 1.2: ROM capacity field) P0 to P3, P6,P7, P8...
Page 24 Performance outline M30240 Group Renesas plans to release the following products in the M30240 group: (1) Support for mask ROM version and one-time PROM version (2) ROM capacity (3) Package • 80P6N-A: Plastic molded QFP (mask ROM version and one-time PROM version) Figure 1.3 shows the type number, memory size and package for the M30240 group.
Page 25: Pin Description
Pin Description M30240 Group 1.1.6 Pin Description Table 1.3 shows the M30240 pin description. Table 1.3: Figure pin description Pin # Name Description CMOS I/O port. This pin also functions as an external trigger for A-D conversion. CMOS I/O port. This pin also functions as the start of frame (SOF) pulse for the USB module.
Page 26 Pin Description M30240 Group Pin # Name Description /LED7 43-50 CMOS I/O port. These pins are capable of driving up to 20mA (peak) for LEDs. ~ P2 /LED0 Power: V = 4.1~ 5.25V CMOS I/O port. This port can also function as the key-on wakeup interrupt KI15. Ground: V = 0V CMOS I/O port.
Page 27: Overview
Overview M30240 Group 1.1.7 Overview The M30240 group is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB) Version 1.1 specification. This device provides interface between a USB-equipped host computer and PC peripherals such as telephones, audio systems, and digital cameras. The M30240 block diagram is shown in Figure 1.4.
Page 28: Operation Of Functional Blocks
Central Processing Unit M30240 Group 1.2 Operation of Functional Blocks The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data, and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as USB, timers, serial I/O, DMAC, CRC calculation circuit, A-D converter, and I/O ports.
Page 29: Frame Base Register (Fb)
Central Processing Unit M30240 Group 1.2.1.3 Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. 1.2.1.4 Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be execut- 1.2.1.5 Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vec- tor table.
Page 30 Central Processing Unit M30240 Group 1.2.1.8.9 Bits 8 to 11: Reserved area 1.2.1.8.10 Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is en- abled.
Page 31: Processor Mode
Processor Mode M30240 Group 1.2.2 Processor Mode Figure 1.7 shows the processor mode registers 0 and 1. Processor mode register 0 (Note ) Symbol Address When reset 0004 (Note) Bit symbol Bit name Function Reserved bit Must always be set to "0" Software reset bit PM03 The device is reset when this bit is set...
Page 32: Memory
Memory M30240 Group 1.2.3 Memory 00000 00400 XXXXX unused yyyyy FFE00 Special page vector table FFFDC Undefined instruction Overflow BRK instruction Type Address xxxxx Address yyyyy Address match Single step M30240M5 F6000 00FFF Watchdog timer M30240M6 00FFF F4000 017FF E0000 M30240ECFP Reset FFFFF...
Page 33: Sfr Map
SFR Map M30240 Group 1.2.4 SFR Map The SFR tables show the peripheral control registers, their addresses, acronyms, and values after reset. Address Register name Acronym Value after reset Figure number 0000 0001 0002 0003 0004 Processor mode register 0 Figure 1.7 0005 Processor mode register 1...
Page 34 SFR Map M30240 Group Address Register name Acronym Value after reset Figure number 0038 DMA1 transfer counter TCR1 Figure 1.56 0039 003A 003B 003C DMA1 control register DM1CON 0 0 0 0 0 ? 0 0 Figure 1.55 003D 003E 003F 0040 0041...
Page 35 SFR Map M30240 Group Address Register name Acronym Value after reset Figure number 0314 USB reserved 0315 USB Endpoint 0 OUT write count EP0WC Figure 1.46 0316 USB reserved 0317 USB reserved 0318 USB reserved 0319 USB Endpoint 1 IN control/status register EP1ICS Figure 1.47 031A...
Page 36 SFR Map M30240 Group Address Register name Acronym Value after reset Figure number 0351 0352 0353 0354 0355 0356 0357 0358 0359 035A 035B 035C 035D 035E 035F 0370 0371 0372 0373 0374 0375 0376 0377 Reserved 0378 UART2 transmit / receive mode register U2MR Figure 1.77 0379...
Page 37 SFR Map M30240 Group Address Register name Acronym Value after reset Figure number Figure 1.63 Timer A2 mode register Figure 1.64 0398 TA2MR Figure 1.65 Figure 1.66 Figure 1.68 Figure 1.63 Timer A3 mode register Figure 1.66 0399 TA3MR Figure 1.65 Figure 1.68 Figure 1.63 Timer A4 mode register...
Page 38 SFR Map M30240 Group Address Register name Acronym Value after reset Figure number 03CC A-D register 6 Figure 1.98 03CD 03CE A-D register 7 Figure 1.98 03CF 03D0 03D1 03D2 03D3 03D4 A-D control register 2 ADCON2 Figure 1.98 03D5 03D6 A-D control register 0 ADCON0...
Page 39: Reset
Reset M30240 Group 1.2.5 Reset There are two types of resets: hardware and software. In both cases, operation is the same after the reset. 1.2.5.1 Hardware reset When the supply voltage is within the range where operation is guaranteed, a reset is effected by hold- ing the reset pin level “L”...
Page 40: Clock-Generating Circuit
Clock-Generating Circuit M30240 Group 1.2.5.2 Software Reset Writing a “1” to bit 3 of the processor mode register 0 (address 0004 ) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset with the following exceptions: The contents of internal RAM are preserved USB registers (0300...
Page 41 Clock-Generating Circuit M30240 Group usb (48MHz) Frequency Synthesizer fsyn Circuit Main clock SIO2 SIO2 FSCCR0=1 SIO2 FSCCR0=0 CM10 “1” Write signal Divider RESET φ BCLK Software reset CM02 Interrupt request level judgment output WAIT instruction CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 CM06=0 CM17,CM16=01 CM06=0...
Page 42 Clock-Generating Circuit M30240 Group • fAD This clock has the same frequency as the main clock and is used for A-D conversion. • fUSB This is the 48mHz clock that is used for USB operation. This clock is generated from the main clock by the frequency synthesizer circuit.
Page 43: Stop Mode
Stop Mode M30240 Group 1.2.7 Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 0007 ) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that V remains above 2V.
Page 44: Power Control
Power Control M30240 Group • Division by 4 mode The main clock is divided by 4 to obtain the internal clock Φ. • Division by 8 mode The main clock is divided by 8 to obtain the internal clock Φ. Note that oscillation of the main clock must have stabilized before transferring from this mode to another mode.
Page 45: Protection
Protection M30240 Group 1.2.11 Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.14 shows the protect register. The values in the processor mode register 0 (address 0004 ), processor mode register 1 (address 0005 ), system clock...
Page 46: Interrupts
Interrupts M30240 Group 1.2.12 Interrupts Table 1.9 and Table 1.10 show the interrupt sources and vector table addresses. When an interrupt is received, the program is executed from the address shown by the respective interrupt vector. The vector table addresses for the interrupts in Table 1.9 are fixed (interrupt vector addresses). These interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts).
Page 47 Interrupts M30240 Group Table 1.10: Interrupt vectors with variable addresses) Vector table addresses Software interrupt number Address(L) to Interrupt source Remarks Address(H) (Note 1) Software interrupt number 0 +0 to +3 BRK instruction Cannot be masked by I flag Software interrupt number 4 +16 to +19 USB Suspend Software interrupt number 6...
Page 48: Interrupt Control Registers
Interrupts M30240 Group 1.2.12.1 Interrupt control registers Peripheral I/O interrupts have their own interrupt control registers. Table 1.11 shows the addresses of the interrupt control registers. Figure 1.16 shows the interrupt control registers. The interrupt request bit is set by hardware to “0” when an interrupt request is received. The interrupt request bit can also be set by software to “0”.
Page 49 Interrupts M30240 Group Interrupt control register When reset Symbol Address SUSPIC 0044 XXXXX000 RSMIC 0046 XXXXX000 BCNIC 004A XXXXX000 DMiIC(i=0, 1) 004B , 004C XXXXX000 KUPIC 004D XXXXX000 ADIC 004E XXXXX000 SiTIC(i=0 to 2) 0051 , 0053 , 004F XXXXX000 SiRIC(i=0 to 2) 0052 , 0054...
Page 50: Interrupt Priority
Interrupts M30240 Group 1.2.12.2 Interrupt priority The order of priority when two or more interrupts are generated simultaneously is determined by both hardware and software. The interrupt priority levels determined by hardware are Reset > NMI > DBC > Watchdog timer > pe- ripheral I/O interrupts >...
Page 51 Interrupts M30240 Group Priority level of each interrupt Level 0 (initial value) INT1 High USB Reset Timer B0 Timer A3 Timer A1 USB Resume USB Suspend USB Function INT0 Timer B1 Timer A4 Timer A2 USB SOF UART1 reception UART0 reception UART2 reception Priority of peripheral I/O interrupts (if priority levels are same)
Page 52: Flag Changes
NMI Interrupt M30240 Group 1.2.12.3 Flag changes When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack pointer (ISP).
Page 53: Key Input Interrupt
Key input interrupt M30240 Group 1.2.14 Key input interrupt If the direction register of any of pin of Port0 or Port1 is set for input and a falling edge is input to that port, a key-input interrupt is generated. A key-input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode.
Page 54: Address Match Interrupt
Address Match Interrupt M30240 Group 1.2.15 Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit.
Page 55 Watchdog Timer M30240 Group The watchdog timer is initialized by writing to the watchdog timer start register (address 000E ) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E Figure 1.21 shows the block diagram of the watchdog timer.
Page 56: Frequency Synthesizer Circuit
Frequency Synthesizer Circuit M30240 Group 1.2.17 Frequency Synthesizer Circuit The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock f that are both a multiple of the external input reference clock f(X ). A block diagram of the circuit is shown in Figure 1.23.
Page 57: Multiplier
Frequency Synthesizer Circuit M30240 Group 1.2.17.2 Multiplier Clock f is a multiplied up version of clock f (See Figure 1.25). The relationship between f and the clock input to the multiplier (f ) from the prescaler is as follows: • f x 2(n+1) where n is the decimal equivalent of the value loaded in FSM.
Page 58 Frequency Synthesizer Circuit M30240 Group The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = “0”), f is held at either a high or low state. When the frequency synthesizer control bit is active (FSC0 = “1”), a lock status (LS = “1”) indicates that f and f are the correct frequency.
Page 59: Universal Serial Bus
Universal Serial Bus M30240 Group 1.2.18 Universal Serial Bus The Universal Serial Bus (USB) has the following features: • Complete USB Specification (version 1.1) Compatibility • Error-handling capabilities • FIFOs: • Endpoint 0:IN/OUT 32-byte • Endpoint 1:IN 128-byteOUT 128-byte • Endpoint 2:IN 32-byteOUT 32-byte •...
Page 60: Usb Interrupts
Universal Serial Bus M30240 Group 1.2.18.1.2 Generic Function Interface The GFI handles all USB standard requests from the host through the control endpoint (endpoint zero), han- dles Bulk, Isochronous and Interrupt transfers through Endpoints 1-4. The GFI handles read pointer reversal for re-transmission the current data set;...
Page 61 Universal Serial Bus M30240 Group 1.2.18.2.1 USB Function Interrupt The USB Function Interrupt can be triggered by 10 sources; many of these may be cause by several different events. Interrupt status flags associated with each source are contained in USBIS1 and USBIS2. Endpoints 1-4 have two interrupt status flags associated with it to control data transfer or to report a STALL/ UNDER_RUN/OVER RUN condition.
Page 62: Usb Endpoint Fifos
Universal Serial Bus M30240 Group 1.2.18.2.4 USB SOF Interrupt The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU generates a USB SOF Interrupt request when a start-of-frame packet is received. Register SOFIC contains the USB SOF Interrupt’s request bit and its interrupt priority select bits, which are used to enable the interrupt and set its software priority level.
Page 63 Universal Serial Bus M30240 Group The status of endpoint 1-4 IN FIFOs for both of the above cases can be obtained from the IN CSR of the cor- responding IN FIFO as shown in Table 1.14 . Table 1.14: TA FIFO Status IN_PKT_RDY TX_NOT_EPT IN FIFO Status...
Page 64: Usb Special Function Registers
Universal Serial Bus M30240 Group 1.2.18.3.3 Interrupt Endpoints Any endpoint can be used for interrupt transfers. For normal interrupt transfers, the interrupt transactions be- have the same as bulk transactions, i.e., no special setting is required. The IN endpoints may also be used to communicate rate feedback information for certain types of isochronous functions.
Page 65 Universal Serial Bus M30240 Group 1.2.18.4.2 USB Control Register The USB Control Register, shown in Figure 1.31, is used to control the USB FCU. This register is not reset by a USB reset signaling. After the USB is enabled (USBC7 set to “1”), a minimum delay of 250ns (three 12 MHz clock periods) is needed before performing any other USB register read/write operations.
Page 66 Universal Serial Bus M30240 Group 1.2.18.4.4 USB Power Management Register The USB Power Management Register, shown in Figure 1.33, is used for power management in the USB FCU. • SUSPEND Detection Flag: When the USB FCU does not detect any bus activity on D+/D- for at least 3ms (and D+/D- are in the J-state), it sets the Suspend Detection Flag and generates an interrupt.
Page 67 Universal Serial Bus M30240 Group 1.2.18.4.5 USB Interrupt Status Registers 1 and 2 USB Interrupt Status Registers 1 and 2, shown in Figure 1.34 and Figure 1.35, are used to indicate the con- dition that caused a USB function interrupt and USB Reset, Suspend and Resume Interrupts to the CPU. A “1”...
Page 68 Universal Serial Bus M30240 Group USB Interrupt Status Register 2 Symbol Address When reset USBIS2 0303 Bit symbol Bit name Function 0 : No interrupt request issued USB Endpoint 4 IN INTST8 1 : Interrupt request issued Interrupt Status Flag USB Endpoint 4 OUT 0 : No interrupt request issued INTST9...
Page 69 Universal Serial Bus M30240 Group 1.2.18.4.6 USB Interrupt Enable Registers 1 and 2 The USB Interrupt Enable Registers 1 and 2, shown in Figure 1.36 and Figure 1.37, are used to enable the corresponding interrupt status conditions that can generate a USB Function Interrupt. When the bit to a cor- responding interrupt condition is “0”, that condition does not generate a USB function interrupt.
Page 70 Universal Serial Bus M30240 Group 1.2.18.4.7 USB Frame Number Registers The USB Frame Number Low Register, shown in Figure 1.38, contains the lower 8 bits of the 11-bit frame number received from the host. The USB Frame Number High Register, shown in Figure 1.39 contains the upper 3 bits of the 11-bit frame number received from the host.
Page 71 Universal Serial Bus M30240 Group 1.2.18.4.9 USB DMAx Request Registers The USB DMAx Request Registers, shown in Figure 1.41 and Figure 1.42, are used to select which USB End- point x FIFO read/write requests are selected as the DMAC channel 0 or channel 1 request source. The USB DMA0 (DMA1) Request Register should have only one bit set at any given time.
Page 72 Universal Serial Bus M30240 Group 1.2.18.4.11 USB Endpoint 0 Control and Status Register The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control and status in- formation of Endpoint 0. • EP0CSR0 (OUT_PKT_RDY): The USB FCU sets this bit to a “1” after it receives a valid SETUP/OUT token from the host. The CPU clears this bit after unloading the packet from the FIFO by writing a “1”...
Page 73 Universal Serial Bus M30240 Group data will be in the FIFO. For this case, because the SETUP_END bit is set near the beginning of the packet when the SETUP PID is encountered and the OUT_PKT_RDY bit is set at the end of the packet, the value read from EP0IN_CSR in the USB functional interrupt routine may only show that the SETUP_END flag as “1”...
Page 74 Universal Serial Bus M30240 Group 1.2.18.4.13 USB Endpoint 0 OUT Write Count Register The USB Endpoint 0 OUT Write Count (WRT CNT) Register, shown in Figure 1.46, contains the number of bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after having successfully received a packet of data from the host.
Page 75 Universal Serial Bus M30240 Group The CPU writes a “1” to this bit to flush the IN FIFO. When there is one packet in the IN FIFO, a flush causes the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO.
Page 76 Universal Serial Bus M30240 Group When endpoint is required to initialize the data toggle sequence bit (i.e. reset to DATA0 for the next data pack- et), the CPU sets this bit to a “1” and then resets it to a “0” to initialize the respective endpoint’s data toggle. Successful initialization of the data toggle sequence bit can only be guaranteed if no active OUT transaction to the respective endpoint is ongoing when the initialization process is taking place.
Page 77 Universal Serial Bus M30240 Group 1.2.18.4.17 USB Endpoint x OUT MAXP Register The USB Endpoint x OUT MAXP Register, shown in Figure 1.50, indicates the maximum packet size (MAXP) of an Endpoint x OUT packet. The default values for endpoints 1-4 are 0 bytes. The setting of this register also affects the configuration of single/dual packet operation.
Page 78: Dmac
DMAC M30240 Group 1.2.19 DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU.Table 1.15 shows the DMAC specifications. Figure 1.53 shows the block diagram of the DMAC. Figure 1.54, Figure 1.55 and Figure 1.56 show the registers used by the DMAC.
Page 79 DMAC M30240 Group Address bus DMA0 source pointer SAR0(20) (addresses 0022 to 0020 DMA0 destination pointer DAR0 (20) (addresses 0026 to 0024 (Note) DMA0 forward address pointer (20) DMA0 transfer counter reload register TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 0029 , 0028 (addresses 0032...
Page 80 DMAC M30240 Group DMAi control register Address Symbol When reset 002C , 003C 00000X00 DMiCON(i=0,1) Bit symbol Bit name Function 0 : 16 bits DMBIT Transfer unit bit select bit 1 : 8 bits Repeat transfer mode 0 : Single transfer DMASL select bit 1 : Repeat transfer...
Page 81 DMAC M30240 Group DMAi source pointer (i = 0, 1) (b19) (b16)(b15) (b8) (b23) Symbol Address When reset SAR0 0022 to 0020 Indeterminate SAR1 0032 to 0030 Indeterminate Transfer count Function specification • Source pointer 00000 to FFFFF Stores the source address Nothing is assigned.
Page 82 DMAC M30240 Group Number of transfer cycles per transfer unit = Number of read cycles x j + Number of write cycles x k Table 1.16: Number of DMAC transfer cycles Single-chip mode Transfer unit Access address Number of read cycles Number of write cycles Even 8-bit transfers (DMBIT=”1”)
Page 83: Timers
Timers M30240 Group 1.2.20 Timers There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function independently. Figure 1.58 shows the block diagram of Timers A and •...
Page 84: Timer A
Timer A M30240 Group 1.2.21 Timer A Figure 1.59, Figure 1.60,Figure 1.61, and Figure 1.62 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: •...
Page 85 Timer A M30240 Group Timer Ai register (Note) Symbol Address When reset (b15) (b8) 0387 ,0386 Indeterminate b0 b7 0389 ,0388 Indeterminate 038B ,038A Indeterminate 038D ,038C Indeterminate 038F ,038E Indeterminate Function Values that can be set • Timer mode 0000 to FFFF Counts an internal count source...
Page 86 Timer A M30240 Group One-shot start flag Symbol Address When reset ONSF 0382 00X00000 Bit symbol Bit name Function Timer A0 one-shot start flag 1 : Timer start TA0OS When read, the value is “0” Timer A1 one-shot start flag TA1OS Timer A2 one-shot start flag TA2OS...
Page 87: Timer Mode
Timer A M30240 Group 1.2.21.1 Timer mode In this mode, the timer counts an internally generated count source. See Table 1.18 below. Figure 1.63 shows the timer Ai mode register in timer mode. Table 1.18: Specifications of timer mode Item Specification Count source f1, f8, f32...
Page 88: Event Counter Mode
Timer A M30240 Group 1.2.21.2 Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two- phase external signal.
Page 89 Timer A M30240 Group Table 1.20: Timer specification in event counter mode (when processing two-phase pulse signal with Timers A2, A3, A4.) Item Specification Count Source •Two-phase pulse signals input to TAi or TAi •Up count or down count can be selected by two-phase pulse signal Count operation •When the timer overflows or underflows, the reload register content is loaded and the timer starts over again (Note 1)
Page 90 Timer A M30240 Group Timer Ai mode register (When not using two-phase pulse signal processing) Address Symbol When reset 0398 to 039A TAiMR(i = 2 to 4) Bit symbol Bit name Function TMOD0 b1 b0 Operation mode select bit 0 1 : Event counter mode TMOD1 0 : Pulse is not output Pulse output function...
Page 91: One-Shot Timer Mode
Timer A M30240 Group 1.2.21.3 One-shot timer mode In this mode, the timer operates only once (See Table 1.21 ). When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.66 shows the Timer Ai mode register in one- shot mode.
Page 92: Pulse-Width Modulation (Pwm) Mode
Timer A M30240 Group 1.2.21.4 Pulse-width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession (See Table 1.22 ). In this mode, the counter functions as either a 16-bit pulse-width modulator or an 8-bit pulse-width modulator. Figure 1.67 shows an example of how a 16-bit pulse-width modulator operates.
Page 93 Timer A M30240 Group Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 0396 to 039A Bit symbol Bit name Function b1 b0 TMOD0 Operation mode 1 1 : PWM mode select bit TMOD1 Must always be "1" in PWM mode) 0 : Falling edge of TAi pin's input signal External trigger select bit...
Page 94: Timer B
Timer B M30240 Group 1.2.22 Timer B Figure 1.70 shows the block diagram of timer B. Figure 1.71 and Figure 1.72 show the Timer B-related registers. Use the Timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. Timer B works in Timer mode only (i.e., the timer counts an in internal count source).
Page 95: Timer Mode
Timer B M30240 Group Timer Bi register (Note) (b15) (b8) b0 b7 Symbol Address When reset 0391 , 0390 Indeterminate 0393 , 0392 Indeterminate 0395 , 0394 Indeterminate Function Values that can be set • Timer mode 0000 to FFFF Counts the timer's period Note: Read and write data in 16-bit units.
Page 96: Uart0 To Uart2
UART0 to UART2 M30240 Group 1.2.23 UART0 to UART2 Serial I/O is configured as three channels: UART0, UART1, and UART2. UART0, UART1, and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.73 shows the block diagram of UART0, UART1, and UART2.
Page 97 UART0 to UART2 M30240 Group Clock synchronous type UART (7 bits) UART (8 bits) Clock UARTi receive register synchronous UART (7 bits) type disabled RxDi UART UART (9 bits) enabled Clock synchronous type UART (8 bits) UART (9 bits) UARTi receive buffer register Address 03A6 MSB/LSB conversion circuit...
Page 98 UART0 to UART2 M30240 Group UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A0 , 03A8 and 0378...
Page 99 UART0 to UART2 M30240 Group UARTi transmit buffer register Symbol Address When reset (b15) (b8) U0TB 03A3 , 03A2 Indeterminate U1TB 03AB , 03AA Indeterminate U2TB 037B , 037A Indeterminate Function Transmit data Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. UARTi receive buffer register (b8) Symbol...
Page 100 UART0 to UART2 M30240 Group UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 , 03A8 Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) Must be fixed to 001 b2 b1 b0 SMD0 Serial I/O mode select bit 1 0 0 : Transfer data 7 bits long b2 b1 b0...
Page 101 UART0 to UART2 M30240 Group UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 , 03AC Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) b1 b0 b1 b0 CLK0 BRG count source 0 0 : f is selected 0 0 : f...
Page 102 UART0 to UART2 M30240 Group UARTi transmit/receive control register 1 Address Symbol When reset 03A5 03AD UiC1(i=0,1) Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) 0 : Transmission disabled 0 : Transmission disabled Transmit enable bit 1 : Transmission enabled 1 : Transmission enabled 0 : Data present in...
Page 103: Clock Synchronous Serial I/O Mode
UART0 to UART2 M30240 Group UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 X0000000 Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) U0IRS UART0 transmit Transmit buffer empty (Tl = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed 1 : Transmission completed...
Page 104 UART0 to UART2 M30240 Group Table 1.25: Specifications of Clock synchronous serial I/O mode Item Specification Transfer data format •Transfer data length: 8 bits •When internal clock is selected (bit 3 at addresses 03A0 , 03A8 , 0378 = “0”): fi/2(n+1) (Note 1) fi = f1, f8, f32 Transfer clock •When external clock is selected (bit 3 at addresses 03A0...
Page 105 UART0 to UART2 M30240 Group Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxD pin outputs a “H”.
Page 106 UART0 to UART2 M30240 Group Example of transit timing (when internal clock is selected) Transfer clock “1” Transmit enable “0” Data is set in UARTi transmit buffer register bit (TE) “1” Transmit buffer empty flag (Tl) “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H”...
Page 107 UART0 to UART2 M30240 Group 1.2.23.1.1 Polarity select function As shown in Figure 1.83, the CLK polarity select bit (bit 6 at addresses 03A4 , 03AC , 037C ) allows se- lection of the polarity of the transfer clock. • When CLK polarity select bit = “0” Note 1: The CLK pin level when not transferring data is “H”.
Page 108 UART0 to UART2 M30240 Group 1.2.23.1.4 Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B0 , bit 5 at address 037D ) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again.
Page 109: Clock Asynchronous Serial I/O (Uart) Mode
UART0 to UART2 M30240 Group 1.2.23.2 Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.27 lists the specifications of the UART mode. Table 1.27: Specifications of UART mode Item Specification...
Page 110 UART0 to UART2 M30240 Group UARTi transmit / receive mode registers Symbol Address When reset UiMR(i=0,1) 03A0 , 03A8 Bit symbol Bit name Function SMD0 b2 b1 b0 Serial I/O mode select bit 1 0 0 : Transfer data 7 bits long SMD1 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long...
Page 111 UART0 to UART2 M30240 Group Figure 1.88 and Figure 1.89 show the typical UART mode transmit and receive timing diagrams. Example of receive timing when tranfer data is 8 bits long (parity disabled, one-stop bit) BRGi count ..source “1” Receive enable bit “0”...
Page 112 UART0 to UART2 M30240 Group Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Transfer clock “1”...
Page 113 UART0 to UART2 M30240 Group 1.2.23.2.1 Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers con- nected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A0 , 03A8 is set to “1”...
Page 114: Clock-Asynchronous Serial I/O Mode (Compliant With The Sim Interface)
UART0 to UART2 M30240 Group 1.2.23.3 Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this func- tion.
Page 115 UART0 to UART2 M30240 Group Transfer clock “1” Transmit enable bit(TE) “0” Note 1 Data is set in UART2 transmit buffer register “1” Transmit buffer empty flag(TI) “0” Transferred from UART2 transmit buffer register to UART2 transmit register Start Parity Stop A “L”...
Page 116 UART0 to UART2 M30240 Group 1.2.23.3.1 Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D ) assigned “1”, you can output an “L” level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal.
Page 117: A-D Converter
A-D Converter M30240 Group 1.2.24 A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P10 to P10 function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7 ) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (V...
Page 118 A-D Converter M30240 Group CKS1=1 φ CKS0=1 A-D conversion rate CKS1=0 CKS0=0 selection VCUT=0 Resistor ladder VCUT=1 Successive conversion register A-D control register 1 (address 03D7 A-D control register 0 (address 03D6 Addresses (03C1 , 03C0 A-D register 0(16) (03C3 , 03C2 A-D register 1(16) (03C5...
Page 119 A-D Converter M30240 Group A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog input pin select bit 0 0 0 : AN is selected 0 0 1 : AN is selected 0 1 0 : AN is selected...
Page 120 A-D Converter M30240 Group A-D control register 2 (Note) Symbol Address When reset ADCON2 03D4 0 0 0 0000XXX0 Bit symbol Bit name Function A-D conversion method 0 : Without sample and hold 1 : With sample and hold select bit Reserved bit Always set to “0”...
Page 121: One-Shot Mode
A-D Converter M30240 Group 1.2.24.1 One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D con- version.Table 1.31 shows the specifications of one-shot mode. Figure 1.99 shows the A-D control reg- ister in one-shot mode.
Page 122: Repeat Mode
A-D Converter M30240 Group 1.2.24.2 Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conver- sion.Table 1.32 shows the specifications of repeat mode. Figure 1.100 shows the A-D control register in repeat mode.
Page 123: Single-Sweep Mode
A-D Converter M30240 Group 1.2.24.3 Single-sweep mode In single-sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.33 shows the specifications of single-sweep mode. Figure 1.101 shows the A-D control register in single-sweep mode. Table 1.33: Single-sweep mode specification Item...
Page 124: Repeat-Sweep Mode 0
A-D Converter M30240 Group 1.2.24.4 Repeat-sweep mode 0 In repeat-sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.34 shows the specifications of repeat-sweep mode 0. Figure 1.102 shows the A-D control register in repeat-sweep mode 0.
Page 125: Repeat-Sweep Mode 1
A-D Converter M30240 Group 1.2.24.5 Repeat-sweep mode 1 In repeat-sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins select- ed using the A-D sweep pin select bit. Table 1.35 shows the specifications of repeat-sweep mode 1. Figure 1.103 show the A-D control in repeat-sweep mode 1.
Page 126: Sample And Hold
A-D Converter M30240 Group 1.2.24.6 Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4 ) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φ AD cycle is achieved with 8-bit resolution and 33 φ...
Page 127: Crc Calculation Circuit
CRC Calculation Circuit M30240 Group 1.2.25 CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register.
Page 128: Programmable I/O Ports
Programmable I/O Ports M30240 Group 1.2.26 Programmable I/O Ports There are 63 programmable I/O ports: P0 to P3, P6 to P8 (excluding P8 ), and P10. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set.
Page 129 Programmable I/O Ports M30240 Group to P3 Pull-up selection Direction register Data bus Port latch to P2 Pull-up selection Direction register Data bus Port latch Drive capacity control register Pull-up selection Direction register “1” Output Data bus Port latch Input respective peripheral functions Drive capacity control register to P0 Pull-up selection...
Page 130 Programmable I/O Ports M30240 Group , P6 , P6 , P8 Pull-up selection Direction register “1” Output Data bus Port latch , P6 , P6 , P6 Pull-up selection Direction register “1” Output Data bus Port latch Input to respective peripheral functions Pull-up selection Direction register “1”...
Page 131 Programmable I/O Ports M30240 Group (Note 2) BYTE BYTE Input (Note 1) (Note 2) CNVss CNVss Input (Note 1) (Note 2) RESET RESET Input (Note 1) Note 1: symbolizes parasitic diode. Note 2: A parasititc diode on the Vcc side is added to the mask ROM version. Do not apply a voltage higher than Vcc to each pin.
Page 132 Programmable I/O Ports M30240 Group Port Pi register Symbol Address When reset Pi (i = 0 to 3,6,7,10) 03E0 , 03E1 , 03E4 , 03E5 Indeterminate 03EC , 03ED , 03F4 Indeterminate Bit symbol Bit name Function Pi_0 Port Pi register Data is input and output to and from Pi_1...
Page 133 Programmable I/O Ports M30240 Group Port 2 Drive Capacity register Symbol Address When reset P2DR 03FA Bit symbol Bit name Function P2DR0 LED drive capacity The N-channel high-drive capacity P2DR1 LED drive capacity is activated for the corresponding bit. P2DR2 LED drive capacity P2DR3 LED drive capacity...
Page 134 Programmable I/O Ports M30240 Group Microcomputer Port P0 to P3, P6-P8, P10 (except P8 3 , P8 5 , P8 6 ) (Input mode) · · · · · · (Input mode) Open (Output mode) Open USB D+ Open USB D- Open Open P8 6 /SOF...
Page 135: Usage Precautions
Precautions M30240 Group 1.3 Usage Precautions 1.3.1 Precautions 1.3.1.1 A-D Converter Connect a capacitor between: the V pin and the AVss pin; AVcc pin and AVss pin; and each analog input pin and AVss pin. • Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
Page 136: Dedicated Input Pins
Precautions M30240 Group 1.3.1.3 Dedicated Input Pins If a dedicated input pin is connected to a power supply different from the supply that Vcc is connected to, a resistor (approximately 1k ohm) should be added between the input pin and the connected power supply.
Page 137: Noise
Precautions M30240 Group • The value of the stack pointer is initialized to 00000 immediately after reset. Accepting an interrupt before setting a value in the stack pointer may cause program runaway. Be sure to set a value in the stack pointer before accepting an interrupt.
Page 138: Timer A (Timer Mode)
Precautions M30240 Group 1.3.1.9 Stop Mode and Wait Mode When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. When entering either wait or stop mode, you must first enable any interrupts you want to cancel the wait or stop.
Page 139: Timer A (Pulse-Width Modulation Mode)
Precautions M30240 Group 1.3.1.13 Timer A (Pulse-width Modulation mode) 1. The Timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode. •...
Page 140 Precautions M30240 Group • When using an isochronous transfer, set the FLUSH bit by: • OUT FIFO data flush: When OUT_PKT_RDY flag is “1”, set the FLUSH bit to “1” • IN FIFO data flush: Use AUTO_FLUSH bit. • Do not write to the USB internal registers (address 0300 -033C ) when the USB clock is disabled in Suspend mode.
Page 141 Precautions M30240 Group Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification sheet (3) ROM data: EPROMs or floppy disks *: In the case of EPROMs, there are sets of EPROMs are required per pattern. *: In the case if floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pat- tern.
Page 142: Specifications
Electrical characteristics M30240 Group 1.4 Specifications 1.4.1 Electrical characteristics Table 1.37: Absolute maximum ratings only, not operating conditions Symbol Parameter Condition Rated Value Unit Supply voltage Vcc=AVcc -0.3 to 6.5 Analog supply voltage -0.3 to 6.5 Port0, Port1, Port2, Port3, Port6, Input voltage -0.3 to Vcc+0.3...
Page 143 Electrical characteristics M30240 Group Table 1.38: Recommended operating conditions (Vcc=4.1~5.25V, Vss=0V, Ta= 0°C∼ 70°C, f(Xin) = 12MHz) Standard Symbol Parameter Unit Supply voltage 5.25 Analog supply voltage Supply voltage Avss Analog supply voltage Port0, Port1, Port2, Port3, Port6, Port7, High input voltage 0.8Vcc Port8,Port10,RESET,V Port0, Port1, Port2, Port3, Port6, Port7,...
Page 144 Electrical characteristics M30240 Group °C∼ °C Table 1.39: Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0 , f(Xin) = 12MHz) Standard Symbol Parameter Measuring condition Unit Port0, Port1, Port2, Port3, Port6, High output voltage Port71, P73,P75,P77,Port8 = -5mA, Vcc=5V (except P85), Port10 High output voltage Port 70,P72,P74,P76,P80 = -10mA, Vcc=5V...
Page 145 Electrical characteristics M30240 Group °C∼ °C Table 1.40: USB Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0 , f(Xin) = 12MHz) Standard Symbol Parameter Measuring Condition Unit I=18.3 mA, RX=33 Ω, VXcap =3.0 V D+, D- I=18.3 mA, RX=33 Ω, VXcap =3.0 V D+, D- Suspend USB suspend mode, internal clock...
Page 146: Timing
Timing M30240 Group 1.4.2 Timing Timing requirements referenced to Vcc = 4.1~5.25V, Vss=0V, Ta= 0°C~70°C unless otherwise specified. Table 1.42: External clock input Standard Symbol Parameter Unit External clock input cycle time 83.3 tw(H) External clock input HIGH pulse width tw(L) External clock input LOW pulse width External clock rise time...
Page 147 Timing M30240 Group Table 1.47: Timer A input (up/down input in event counter mode) Standard Symbol Parameter Unit input cycle time 2000 input HIGH pulse width 1000 input LOW pulse width 1000 tsu( input setup time input hold time Table 1.48: A-D trigger input Standard Symbol...
Page 148 Timing Diagram M30240 Group 1.4.3 Timing Diagram c(TA) w(TAH) input w(TAL) c(UP) w(UPH) input w(UPL) input (Up/down input) During event counter mode input –UP) su(UP–T (When count on falling edge is selected) input (When count on rising edge is selected) c(AD) w(ADL) input...
Page 149: Applications
Frequency Synthesizer M30240 Group 1.5 Applications 1.5.1 Frequency Synthesizer This section presents the recommended method of setting up and using the frequency synthesizer that generates the 48MHz clock needed by the USB FCU and the DC-DC converter that provides power to the D+/D- drivers.
Page 150: Set Up Of Frequency Synthesizer And Dc-Dc Converter
Frequency Synthesizer M30240 Group 1.5.1.2 Set up of Frequency Synthesizer and DC-DC Converter USBC5 Frequency f(Xin) DC-DC Converter Synthesizer current (enable) enable lock enable mode USBC3 USBC4 Ext Cap (enable) 2.2 µF 0.1 µF 27-33 Ω USB Transceiver USB FCU 27-33 Ω...
Page 151: Set Up After Usb Reset Signaling Detected
Frequency Synthesizer M30240 Group Enable PLL RESET Wait 2 Enable DC-DC converter USBC4 Wait (C+1) Enable USB Clock USBC5 Wait at least 4 cycles of Φ USBC7 Enable USB FCU Figure 1.118: PLL and DC-DC Converter Set Up Timing after Hardware Reset 1.5.1.3.1 Precautions after Software Reset A software reset occurs after writing a ‘1’...
Page 152: Set Up After Usb Resume Signaling Detected
Frequency Synthesizer M30240 Group • Change the DC-DC converter from high current mode to low current mode by setting USBC3 (bit 3 of the USBC) to a “1” • Disable the USB clock by setting USBC5 (bit 5 of USBC) to a “0”. Once the USB clock is disabled, registers internal to the USB FCU should not be written to.
Page 153: Attach/Detach Function
Attach/Detach Function M30240 Group 1.5.2 Attach/Detach Function The Attach/Detach Function can be used to attach or detach a USB function from the host without disconnecting the cable. When attaching a USB function, the connect registers should be set to 03 the same time on or before the DC-DC Converter is enabled.
Page 154: Usb Transceiver
USB Transceiver M30240 Group 1.5.4 USB Transceiver When using the on-chip voltage converter to supply the necessary 3.3V to the driver circuit, a capacitor network must be connected between Ext. Cap (pin 6) and V (pin 13). Two capacitors are required as shown in Figure 1.21.
Page 155: Programming Notes
Programming Notes M30240 Group 1.5.5 Programming Notes 1.5.5.1 Accessing USB IN/OUT Control and Status Registers Do not use read-modify-write instruction on these registers because they contain control and status bits that can be changed by both hardware and software. There is a possibility that using a read-mod- ify-write instruction might cause incorrect data to be written back to these registers.
Page 156: Usb Consecutive Set Address
Programming Notes M30240 Group Below is an example of how to set/reset the ISO bit of the IN CSR register (for initializing the respective endpoint as an isochronous endpoint): [R1L] = [EPiICS].B OR.B #0AH, R1L ;set ISO bit = 1, write “1” back to UNDER_RUN bit AND.B #0FEH, R1L ;write “0”...
Page 157: Chapter 2: Peripheral Functions Usage
Chapter 2 Peripheral Functions Usage...
Page 158: Protect
Protect M30240 Group 2.1 Protect 2.1.1 Overview 'Protect' is a function that causes a value held in a register to be unchanged even when a program runs away. The following is an overview of the protect function: (1) Registers affected by the protect function The registers affected by the protect function are: •...
Page 159 Protect M30240 Group (1) Clearing the protect (set to write-enabled state) Protect register [Address 000A PRCR Enables writing to system clock control registers 0 and 1 (addresses 0006 and 0007 and frequency synthesizer registers (address 03DB to 03DF 1 : Write-enabled Enables writing to processor mode registers 0 and 1 0 : Write-inhibited 1 : Write-enabled...
Page 160: Timer A
Timer A M30240 Group 2.2 Timer A 2.2.1 Overview The following is an overview for Timer A, a 16-bit timer. 2.2.1.1 Mode Timer A operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which con- trols the count start/stop according to the input signal from a port.
Page 161 Timer A M30240 Group (d) Pulse width modulation (PWM) mode In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or 8-bit variable-period mode can be selected. The trigger for initiating output can also be selected. Please refer to the one-shot timer mode explanation for details, as the operation is identical.16-bit •...
Page 162 Timer A M30240 Group 2.2.1.8 Registers related to Timer A Figure 2.3 shows the memory map of Timer A-related registers. Figure 2.4, Figure 2.5, and Figure 2.6 show Timer A-related registers. 0055 Timer A0 interrupt control register TA0IC 0056 Timer A1 interrupt control register TA1IC 0057 Timer A2 interrupt control register...
Page 163 Timer A M30240 Group Timer Ai register (Note) Symbol Address When reset 0387 , 0386 Indeterminate 0389 , 0388 Indeterminate (b15) (b8) b0 b7 038B , 038A Indeterminate 038D , 038C Indeterminate 038F , 038E Indeterminate Function Values that can be set •...
Page 164 Timer A M30240 Group One-shot start flag Symbol Address When reset ONSF 0382 00X00000 Bit symbol Bit name Function TA0OS Timer A0 one-shot start flag 1 : Timer start When read, the value is “0” TA1OS Timer A1 one-shot start flag TA2OS Timer A2 one-shot start flag TA3OS...
Page 165: Operation
Timer A M30240 Group 2.2.2 Operation 2.2.2.1 Timer mode In timer mode, select functions from those listed in Table 2.1 . An example using the indicated options is described below. Figure 2.7 shows the operation timing, and Figure 2.8 shows the set-up proce- dure.
Page 166 Timer A M30240 Group Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA pin is a normal port pin) iOUT Gate function select bit...
Page 167: Timer Mode With Gate Functions Selected
Timer A M30240 Group 2.2.2.2 Timer Mode with Gate Functions Selected In timer mode, select functions from those listed in Table 2.2. An example using the indicated options is described below. Figure 2.9 shows the operation timing, and Figure 2.10 shows the set-up procedure. Table 2.2: Timer A timer mode and gate functions Item...
Page 168 Timer A M30240 Group Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA pin is a normal port pin) iOUT Gate function select bit...
Page 169: Timer Mode With Pulse-Output Function Selected
Timer A M30240 Group 2.2.2.3 Timer Mode with Pulse-output Function Selected In timer mode, select functions from those listed in Table 2.3 . An example using the indicated options is described below. Figure 2.11 shows the operation timing, and Figure 2.12 shows the set-up proce- dure.
Page 170 Timer A M30240 Group Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of timer mode 1 : Pulse is output (Note) (TA pin is a pulse output pin) iOUT Gate function select bit b4 b3...
Page 171: Event Counter Mode With Reload Type Selected
Timer A M30240 Group 2.2.2.4 Event Counter Mode with Reload Type Selected In event counter mode, select functions from those listed in Table 2.4 . An example using the indicated options is described below. Figure 2.13 shows the operation timing, and Figure 2.14 shows the set-up procedure.
Page 172 Timer A M30240 Group Selecting event counter mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TA pin is a normal port pin) iOUT Count polarity select bit...
Page 173: Event Counter Mode With Free-Run Type Selected
Timer A M30240 Group 2.2.2.5 Event Counter Mode with Free-run Type Selected In event counter mode, select functions from those listed in Table 2.5 . An example using the indicated options is described below. Figure 2.15 shows the operation timing, and Figure 2.16 shows the set-up procedure.
Page 174 Timer A M30240 Group Selecting event counter mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TA pin is a normal port pin) iOUT Count polarity select bit...
Page 175: Two-Phase Pulse Signal Process In Event Counter Mode With Normal Mode Selected
Timer A M30240 Group 2.2.2.6 Two-phase Pulse Signal Process in Event Counter Mode with Normal Mode Selected In processing 2-phase pulse signals in event counter mode, select functions from those listed in Table 2.6 . An example using the indicated options is described below. Figure 2.17 shows the operation timing, and Figure 2.18 shows the set-up procedure.
Page 176 Timer A M30240 Group Selecting event counter mode and functions Timer Ai mode register (i= 2, 3) [Address 0398 , 0399 TAiMR (i= 2, 3) Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0”...
Page 177: Two-Phase Pulse Signal Process In Event Counter Mode With Multiply-By-4 Mode Selected
Timer A M30240 Group 2.2.2.7 2-phase pulse signal process in event counter mode with Multiply-by-4 mode selected In processing 2-phase pulse signals in event counter mode, select functions from those listed in Table 2.7 . An example using the indicated options is described below. Figure 2.19 shows the operation timing and Figure 2.20 shows the set-up procedure.
Page 178 Timer A M30240 Group Selecting event counter mode and functions Timer Ai mode register (i= 3, 4) [Address 0399 , 039A TAiMR (i= 3, 4) Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0”...
Page 179: One-Shot Timer Mode
Timer A M30240 Group 2.2.2.8 One-shot timer mode In one-shot timer mode, select functions from those listed in Table 2.9 . An example using the indicated options is described below. Figure 2.21 shows the operation timing, and Figure 2.22 shows the set-up procedure.
Page 180 Timer A M30240 Group Selecting one-shot timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output External trigger select bit When internal trigger is selected, this bit can be “1”...
Page 181: One-Shot Timer Mode - External Trigger Selected
Timer A M30240 Group 2.2.2.9 One-shot timer mode - External trigger selected In one-shot timer mode, select functions from those listed in Table 2.10 . An example using the indicated options is described below. Figure 2.23 shows the operation timing, and Figure 2.24 shows the set-up procedure.
Page 182 Timer A M30240 Group Selecting one-shot timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output External trigger select bit 1 : Rising edge of TAi pin's input signal...
Page 183: Pulse Width Modulation Mode - 16-Bit Pwm Mode Selected
Timer A M30240 Group 2.2.2.10 Pulse width modulation mode - 16-bit PWM mode selected In pulse width modulation mode, select functions from those listed in Table 2.11 . An example using the indicated options is described below. Figure 2.25 shows the operation timing, and Figure 2.26 shows the set-up procedure.
Page 184 Timer A M30240 Group Selecting PWM mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 1 : Rising edge of TAi pin's input signal (Note 1) Trigger select bit...
Page 185: Pulse Width Modulation Mode - 8-Bit Pwm Mode Selected
Timer A M30240 Group 2.2.2.11 Pulse width modulation mode - 8-bit PWM mode selected In pulse width modulation mode, select functions from those listed in Table 2.12 . An example using the indicated options is described below. Figure 2.27 shows the operation timing, and Figure 2.28 shows the set-up procedure.
Page 186 Timer A M30240 Group Selecting PWM mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 0 : Falling edge of TAi pin's input signal (Note 1) Trigger select bit...
Page 187: Precautions
Timer A M30240 Group 2.2.3 Precautions 2.2.3.1 Timer mode (1) At reset, the count start flag is set to “0”. Set a value in the Timer Ai register, then set the flag to “1”. (2) Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter.
Page 188: One-Shot Timer Mode
Timer A M30240 Group (2) Up count (1) Down count Reload Reload Counter value Counter value n – 1 n + 1 FFFD FFFE FFFF (Hex.) (Hex.) Read value Read value n – 1 FFFD FFFE FFFF 0000 n + 1 FFFF (Hex.) (Hex.)
Page 189: Pulse-Width Modulation Mode
Timer A M30240 Group “H” Trigger input pin input signal “L” Count source One-shot pulse output from TAi Start one-shot pulse output Note: The above applies when an external trigger (falling edge of TAi pin input signal) is selected. Figure 2.32: One-shot timer delay 2.2.3.4 Pulse-width modulation mode (1) At reset, the count start flag is set to “0”.
Page 190: Timer B
Timer B M30240 Group 2.3 Timer B 2.3.1 Overview The following is an overview for Timer B, a 16-bit timer. 2.3.1.1 Mode Timer B operates only in timer mode: • The internal count source is counted See section 2.3.2.1 2.3.1.2 Count source An internal count source can be selected from f1, f8, f32 are clocks obtained by dividing the CPU main clock by 1, 8, and 32 respectively.
Page 191 Timer B M30240 Group Timer Bi mode register Symbol Address When reset TBiMR(i = 0 to 2) 039B to 039D 00XX0000 Bit symbol Bit name Function TMOD0 b1 b0 Operation mode select bit 0 0 : Timer mode TMOD1 Invalid in timer mode. Can be either "0" or "1". Fixed to "0"...
Page 192: Operation
Timer B M30240 Group 2.3.2 Operation 2.3.2.1 Timer mode In timer mode, select functions from those listed in Table 2.13 . An example using the indicated options is described below. Figure 2.36 shows the operation timing, and Figure 2.37 shows the set-up procedure.
Page 193 Timer B M30240 Group Selecting timer mode and functions Timer Bi mode register (i=0 to 2) [Address 039B to 039D TBiMR (i=0 to 2) Selection of timer mode Invalid in timer mode Can be “0” or “1” Fixed to “0” in timer mode ( i = 0) This bit can neither be set nor reset (i = 1, 2) Invalid in timer mode Count source select bit...
Page 194: Precautions
Timer B M30240 Group 2.3.3 Precautions 2.3.3.1 Timer mode (1) At reset, the count start flag is set to “0”. Set a value in the Timer Bi register, then set the flag to “1”. (2) Reading the Timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter.
Page 195: Clock-Synchronous Serial I/O
Clock-Synchronous Serial I/O M30240 Group 2.4 Clock-Synchronous Serial I/O 2.4.1 Overview Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The following is an overview of the clock-synchronous serial I/O. 2.4.1.1 Transmission/reception format 8-bit data 2.4.1.2 Transfer rate If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit rate generator division, becomes the transfer rate.
Page 196 Clock-Synchronous Serial I/O M30240 Group The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from: • CTS/RTS functions disabled CTS/RTS pin is a programmable I/O port. • CTS function only enabled CTS/RTS pin performs the CTS function. •...
Page 197 Clock-Synchronous Serial I/O M30240 Group (g) Function for choosing a transmission interrupt factor. The timing to generate a transmission interrupt can be selected from the following: the instant the transmission buffer is emptied or the instant the transmission register is emptied. When transmission buffer empty timing is selected, an interrupt occurs when the transmitted data is moved from the trans- mission buffer to the transmission register.
Page 198 Clock-Synchronous Serial I/O M30240 Group 2.4.1.8 Registers related to the serial I/O Figure 2.39 shows the memory map of serial I/O-related registers, and Figure 2.40, Figure 2.41, Figure 2.42, Figure 2.43, and Figure 2.44 show serial I/O-related registers. 004F UART2 transit interrupt control register S2TIC 0050 UART2 receive interrupt control register...
Page 199 Clock-Synchronous Serial I/O M30240 Group UARTi transmit buffer register Symbol Address When reset (b15) (b8) U0TB 03A3 , 03A2 Indeterminate U1TB 03AB , 03AA Indeterminate U2TB 037B , 037A Indeterminate Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The values are indeterminate when read. UARTi receive buffer register (b8) (b15)
Page 200 Clock-Synchronous Serial I/O M30240 Group UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 , 03A8 Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) Must be fixed to 001 b2 b1 b0 SMD0 Serial I/O mode select bit 1 0 0 : Transfer data 7 bits long b2 b1 b0...
Page 201 Clock-Synchronous Serial I/O M30240 Group UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 , 03AC Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) b1 b0 b1 b0 CLK0 BRG count source 0 0 : f is selected 0 0 : f...
Page 202 Clock-Synchronous Serial I/O M30240 Group UARTi transmit/receive control register 1 Address Symbol When reset 03A5 03AD UiC1(i=0,1) Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) Transmit enable bit 0 : Transmission disabled 0 : Transmission disabled 1 : Transmission enabled 1 : Transmission enabled Transmit buffer...
Page 203 Clock-Synchronous Serial I/O M30240 Group UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 X0000000 Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) U0IRS UART0 transmit 0 : Transmit buffer empty (Tl = 1) Transmit buffer empty (Tl = 1) 1 : Transmission completed 1 : Transmission completed...
Page 204: Operation
Clock-Synchronous Serial I/O M30240 Group 2.4.2 Operation 2.4.2.1 Transmission in clock-synchronous serial I/O mode In transmitting data in clock-synchronous serial I/O mode, select functions from those listed in Table 2.14. An example using the indicated options is described below. Figure 2.46 shows the operation timing, and Figures 2.47 and 2.48 show the set-up procedures.
Page 205 Clock-Synchronous Serial I/O M30240 Group Example of Wiring Microcomputer Receiver side IC CLKi CTSi Port Example of Operation (1) Transmission enabled (4) Transmission is complete (5) Transmit next data (2) Confirming CTS (3) Start transmission Tc Transfer clock “1” Transmit enable bit (TE) “0”...
Page 206 Clock-Synchronous Serial I/O M30240 Group Setting UARTi transmit/receive mode register (i=0 to 2) UART0 transmit/receive mode register UART2 transmit/receive mode register [Address U0MR 03A0 [Address U2MR 0 3 7 8 UART1 transmit/receive mode register Must be fixed to “001” [Address U1MR 03A8 Internal/external clock select bit...
Page 207 Clock-Synchronous Serial I/O M30240 Group Continued from the previous page Setting UARTi bit rate generator (i = 0 to 2) UARTi bit rate generator (i = 0 to 2) [Address 03A1 , 03A9 , 0379 UiBRG (i = 0 to 2) Can be set from 00 to FF (Note)
Page 208: Transfer Clock Output From Multiple Pins Function Selected
Clock-Synchronous Serial I/O M30240 Group 2.4.2.2 Transfer clock output from multiple pins function selected In transmitting data in clock-synchronous serial I/O mode, select functions from those listed in Table 2.15 . An example using the indicated options is described below. Figure 2.48 shows the operation timing, and Figure 2.49 and Figure 2.50 show the set-up procedures.
Page 209 Clock-Synchronous Serial I/O M30240 Group Example of Wiring Microcomputer CLKS Note: This applies when performing transmission with an internal clock selected and in the clock synchronous serial I/O mode only. Example of Operation (1) Transmission enabled (3) Transmission is complete (2) Start transmission (4) Clock switched Transfer clock...
Page 210 Clock-Synchronous Serial I/O M30240 Group Setting UART1 transmit/receive mode register UART1 transmit/receive mode register [Address 03A8 U1MR Must be fixed to “001” Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0”...
Page 211 Clock-Synchronous Serial I/O M30240 Group Continued from the previous page Setting UART1 bit rate generator UART1 bit rate generator [Address 03A9 U1BRG (Note) Can be set from 00 to FF Note: Write to UARTi bit rate generator when transmission/reception is stopped. Transmission enabled UART1 transmit/receive control register 1 [Address 03AD U1C1...
Page 212: Reception In Clock-Synchronous Serial I/O Mode
Clock-Synchronous Serial I/O M30240 Group 2.4.2.3 Reception in clock-synchronous serial I/O mode For receiving data in clock-synchronous serial I/O mode, select functions from those listed in Table 2.16 An example using the indicated options is described below. Figure 2.51 shows the operation timing, and Figure 2.52 and Figure 2.53 show the set-up procedures.
Page 213 Clock-Synchronous Serial I/O M30240 Group Example of wiring Transmitter side IC Microcomputer CLKi RTSi Port Example of operation (1) Reception enabled (3) Reception is complete (2) Start reception (4) Read of reception data “1” Receive enable bit (RE) “0” “1” Transmit enable bit (TE) “0”...
Page 214 Clock-Synchronous Serial I/O M30240 Group Setting UARTi transmit/receive mode register (i=0 to 2) UART0 transmit/receive mode register UART2 transmit/receive mode register [Address U0MR 03A0 [Address U2MR 0 3 7 8 UART1 transmit/receive mode register Must be fixed to “001” U1MR [Address 03A8 Must be fixed to “001”...
Page 215 Clock-Synchronous Serial I/O M30240 Group Continued from the previous page Reception enabled UARTi transmit/receive control register 1(i = 0 to 2) [Address 03A5 , 03AD , 037D UiC1 (i = 0 to 2) Transmit enable bit 1 : Transmit enabled Receive enable bit 1 : Receive enabled Writing dummy data...
Page 216: Precautions
Clock-Synchronous Serial I/O M30240 Group 2.4.3 Precautions 2.4.3.1 Transmission/Reception With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side that the reception has become ready.
Page 217 Clock-Synchronous Serial I/O M30240 Group (5) With an external clock selected, perform the following set-up procedure with the CLKi pin input lev- el = “H” if the CLK polarity select bit = “0,” or with the CLKi pin input level = “L” if the CLK polarity select bit = “1”: 1.
Page 218: Clock-Asynchronous Serial I/O (Uart)
Clock-Asynchronous Serial I/O M30240 Group 2.5 Clock-Asynchronous Serial I/O (UART) 2.5.1 Overview UART handles communications by means of character-by-character synchronization. The transmission side and the reception side are independent of each other, so full-duplex communication is possible. The following is an overview of the clock-asynchronous serial I/O. 2.5.1.1 Transmission/reception format Figure 2.55 shows the transmission/reception format, and Table 2.16 shows the names and functions...
Page 219 Clock-Asynchronous Serial I/O M30240 Group 2.5.1.2 Transfer rate The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the transfer rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input from the CLK pin.
Page 220 Clock-Asynchronous Serial I/O M30240 Group 2.5.1.3 Error detection In clock-asynchronous serial I/O mode, the errors that can be detected are shown in Table 2.19 . Table 2.19: Error detection Type of error Description Flag “ON” when How to clear the flag •...
Page 221 Clock-Asynchronous Serial I/O M30240 Group When using clock-asynchronous serial I/O, choose one of three types of CTS/RTS functions. • CTS/RTS functions disabled CTS/RTS pin is a programmable I/O port. • CTS function only enabled CTS/RTS pin performs the CTS function. •...
Page 222 Clock-Asynchronous Serial I/O M30240 Group 2.5.1.8 Registers related to the serial I/O Figure 2.56 shows the memory map of serial I/O-related registers, and Figure 2.57, Figure 2.58, Figure 2.59, Figure 2.60, and Figure 2.61 show UARTi-related registers. 004A Bus collision detection interrupt control register BCNIC 004F UART2 transit interrupt control register...
Page 223 Clock-Asynchronous Serial I/O M30240 Group UARTi transmit buffer register Symbol Address (b15) (b8) When reset U0TB 03A3 , 03A2 Indeterminate U1TB 03AB , 03AA Indeterminate U2TB 037B , 037A Indeterminate Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turn out to be indeterminate. UARTi receive buffer register (b15) (b8)
Page 224 Clock-Asynchronous Serial I/O M30240 Group UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 , 03A8 Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) Must be fixed to 001 b2 b1 b0 SMD0 Serial I/O mode select bit 1 0 0 : Transfer data 7 bits long b2 b1 b0...
Page 225 Clock-Asynchronous Serial I/O M30240 Group UARTi transmit/receive control register 0 Address Symbol When reset 03A4 , 03AC UiC0(i=0,1) Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) b1 b0 b1 b0 CLK0 BRG count source 0 0 : f is selected 0 0 : f...
Page 226 Clock-Asynchronous Serial I/O M30240 Group UARTi transmit/receive control register 1 Address Symbol When reset 03A5 03AD UiC1(i=0,1) Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) Transmit enable bit 0 : Transmission disabled 0 : Transmission disabled 1 : Transmission enabled 1 : Transmission enabled Transmit buffer...
Page 227 Clock-Asynchronous Serial I/O M30240 Group UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 X0000000 Function Function Bit name (During clock synchronous symbol (During UART mode) serial I/O mode) U0IRS UART0 transmit 0 : Transmit buffer empty (Tl = 1) Transmit buffer empty (Tl = 1) 1 : Transmission completed 1 : Transmission completed...
Page 228: Operation
Clock-Asynchronous Serial I/O M30240 Group 2.5.2 Operation 2.5.2.1 Transmission in UART mode For transmitting data in UART mode, select functions from those listed in Table 2.20 . An example using the indicated options is described below. Figure 2.62 shows the operation timing, and Figure 2.63 and Figure 2.64 show the set-up procedures.
Page 229 Clock-Asynchronous Serial I/O M30240 Group Example of wiring Microcomputer Receiver side IC CTSi Port Example of operation When confirming stop bit, transfer clock is stopped momentarily because CTS = "H". The transfer clock is started again to begin transmitting immediately after confirming CTS = "L". Transfer clock (1) Transmission enabled (4) Confirm stop bit...
Page 230 Clock-Asynchronous Serial I/O M30240 Group Setting UARTi transmit/receive mode register (i=0 to 2) UART0 transmit/receive mode register UART2 transmit/receive mode register U0MR [Address 03A0 U2MR [Address 0378 UART1 transmit/receive mode register U1MR [Address 03A8 Serial I/O mode select bit Serial I/O mode select bit b2 b1 b0 b2 b1 b0 1 0 1 : Transfer data 8 bits long...
Page 231 Clock-Asynchronous Serial I/O M30240 Group Continued from the previous page Setting UARTi bit rate generator (i = 0 to 2) UARTi bit rate generator (i = 0 to 2) [Address 03A1 , 03A9 , 0379 UiBRG (i = 0 to 2) Can be set from 00 to FF (Note)
Page 232: Reception In Uart Mode
Clock-Asynchronous Serial I/O M30240 Group 2.5.2.2 Reception in UART mode For receiving data in UART mode, select functions from those listed in Table 2.21 . An example using the indicated options is described below. Figure 2.65 shows the operation timing, and Figure 2.66 and Figure 2.67 show the set-up procedures.
Page 233 Clock-Asynchronous Serial I/O M30240 Group Example of wiring Microcomputer Transmitter side IC RTSi Port Example of operation (4) Data is read (1) Reception enabled (3) Receiving is (2) Start reception completed BRGi's count source Receive enable “1” “0” Start bit Stop bit Sampled “L”...
Page 234 Clock-Asynchronous Serial I/O M30240 Group Setting UARTi transmit/receive mode register (i=0 to 2) UART0 transmit/receive mode register [Address UART2 transmit/receive mode register U0MR 03A0 UART1 transmit/receive mode register [Address U2MR 0 3 7 8 [Address U1MR 03A8 Serial I/O mode select bit Serial I/O mode select bit b2 b1 b0 b2 b1 b0...
Page 235 Clock-Asynchronous Serial I/O M30240 Group Continued from the previous page Setting UARTi bit rate generator(i = 0 to 2) UARTi bit rate generator (i = 0 to 2) [Address 03A1 , 03A9 , 0379 UiBRG (i = 0 to 2) Can be set from 00 to FF (Note)
Page 236: Transmission Compliant With Sim Interface
Clock-Asynchronous Serial I/O M30240 Group 2.5.2.3 Transmission compliant with SIM interface For transmitting data in UART mode (compliant with SIM interface), select functions from those listed in Table 2.22 . An example using the indicated options is described below. Figure 2.68 shows the operation timing, and Figure 2.69 and Figure 2.70 show the set-up procedures.
Page 237 Clock-Asynchronous Serial I/O M30240 Group Example of wiring Microcomputer SIM card Example of operation (1) Transmission enabled (3) Confirm stop bit (5) Dispose parity error (2) Start transmission (4) Start transmission Transfer clock “1” Transmit enable bit (TE) (Note 1) “0”...
Page 238 Clock-Asynchronous Serial I/O M30240 Group Setting UART2 transmit/receive mode register UARTi transmit/receive mode register [Address 0378 0 1 1 U2MR Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Must be fixed to “0” in UART mode Stop bit length select bit 0 : One stop bit Odd/even parity select bit (Valid when bit 6 = “1”)
Page 239 Clock-Asynchronous Serial I/O M30240 Group Continued from the previous page Setting UART2 bit rate generator UART2 bit rate generator [Address 0379 U2BRG Can be set from 00 to FF (Note) Note: Write to UARTi bit rate generator when transmission/reception is halted. Reception enabled UART2 transmit/receive control register 1 [Address 037D U2C1...
Page 240: Reception Compliant With Sim Interface
Clock-Asynchronous Serial I/O M30240 Group 2.5.2.4 Reception compliant with SIM interface For receiving data in UART mode (compliant with SIM interface), select functions from those listed in Table 2.23 . An example using the indicated options is described below. Figure 2.71 shows the operation timing, and Figure 2.72 and Figure 2.73 show the set-up procedures.
Page 241 Clock-Asynchronous Serial I/O M30240 Group Example of wiring Microcomputer SIM card Example of operation (1) Reception enabled (3) Receiving is completed (5) Parity error occurred (2) Start reception (4) Data is read Transfer clock “1” Receive enable (RE) “0” Parity Stop Start (Note)
Page 242 Clock-Asynchronous Serial I/O M30240 Group Setting UART2 transmit/receive mode register UART2 transmit/receive mode register [Address 0378 0 1 1 U2MR Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Must be fixed to “0” in UART mode Stop bit length select bit 0 : One stop bit Odd/even parity select bit (Valid when bit 6 = “1”)
Page 243 Clock-Asynchronous Serial I/O M30240 Group Continued from the previous page Setting UART2 bit rate generator UART2 bit rate generator [Address 0379 U2BRG Can be set from 00 to FF (Note) Note: Write to UART2 bit rate generator when transmission/reception is halted. Reception enabled UART2 transmit/receive control register 1 [Address 037D U2C1...
Page 244: Sim Interface Compliance
Clock-Asynchronous Serial I/O M30240 Group 2.5.3 SIM Interface Compliance In conforming to the SIM interface, the UART clock signal within the SIM card needs to conform to the UART2 clock signal within the microprocessor. Two examples are given here as means of generating a UART2 clock signal within the microprocessor.
Page 245 Clock-Asynchronous Serial I/O M30240 Group Table 2.24: UART2 bit rate adjustment factor UART2 bit UART2 bit SIM Card SIM Card Bit rate rate Bit rate rate internal clock internal clock Generator Generator F(Hz) F(Hz) set value set value 1116 1116 2232 1488 4464...
Page 246 Clock-Asynchronous Serial I/O M30240 Group Table 2.25: Timer Ai register adjustment factor SIM Card SIM Card Bit rate Timer Aj Bit rate Timer Aj internal clock internal clock value value F(Hz) F(Hz) 1116 1116 2232 1488 4464 1115 2976 8928 2231 1/16 5952...
Page 247: A-D Converter
A-D Converter M30240 Group 2.6 A-D Converter 2.6.1 Overview The A-D converter used in the M16C/24 group operates on a successive approximation basis. The following is an overview of the A-D converter. 2.6.1.1 Modes The A-D converter operates in one of five modes: (a) One-shot mode Carries out A-D conversion on the input level on one specified pin only once.
Page 248 A-D Converter M30240 Group 2.6.1.4 Functions selection (a) Sample & Hold function The Sample & Hold function samples the input voltage when the A-D conversion starts and carries out an A-D conversion on the voltage sampled. When the A-D conversion starts, the input voltage is sam- pled for 3 cycles of the operation clock.
Page 249 A-D Converter M30240 Group 2.6.1.7 A-D converter and related registers Figure 2.75 shows the memory map of A-D converter-related registers, and Figure 2.76, Figure 2.77, and Figure 2.78 show A-D converter-related registers. 004E A-D conversion interrupt control register ADIC 03C0 A-D register 0 03C1 03C2...
Page 250 A-D Converter M30240 Group A-D control register 1 (Note) A-D control register 1 (Note) Symbol Symbol Address Address When reset When reset ADCON1 ADCON1 03D7 03D7 Bit symbol Bit symbol Bit name Bit name Function Function When single sweep and repeat sweep When single sweep and repeat sweep mode 0 are selected mode 0 are selected...
Page 251: Operation
A-D Converter M30240 Group 2.6.2 Operation 2.6.2.1 One-shot mode In one-shot mode, select functions from those listed in Table 2.27 . An example using the indicated options is described below. Figure 2.79 shows the operation timing, and Figure 2.80 shows the set-up procedure.
Page 252 A-D Converter M30240 Group Selecting Sample and hold A-D control register 2 [Address 03D4 0 0 0 ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 A-D control register 1 [Address 03D7 A-D control register 0 [Address 03D6 ADCON1 ADCON0...
Page 253: One-Shot Mode, External Trigger Selected
A-D Converter M30240 Group 2.6.2.2 One-shot mode, external trigger selected In one-shot mode, select functions from those listed in Table 2.28 . An example using the indicated options is described below. Figure 2.81 shows the timing chart, and Figure 2.82 shows the set-up procedure.
Page 254 A-D Converter M30240 Group Selecting sample and hold A-D control register 2 [Address 03D4 0 0 0 ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 A-D control register 1 [Address 03D7 A-D control register 0 [Address 03D6 ADCON1 ADCON0...
Page 255: Repeat Mode
A-D Converter M30240 Group 2.6.2.3 Repeat mode In repeat mode, select functions from those listed in Table 2.29 . An example using the indicated options is described below. Figure 2.83 shows the timing chart, and Figure 2.84 shows the set-up procedure. Table 2.29: A-D converter in repeat mode functions Item...
Page 256 A-D Converter M30240 Group Selecting Sample and hold A-D control register 2 [Address 03D4 ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 A-D control register 1 [Address 03D7 A-D control register 0 ADCON1 [Address 03D6...
Page 257: Single-Sweep Mode
A-D Converter M30240 Group 2.6.2.4 Single-sweep mode In single-sweep mode, select functions from those listed in Table 2.30 . An example using the indicated options is described below. Figure 2.85 shows the timing chart, and Figure 2.86 shows the set-up procedure.
Page 258 A-D Converter M30240 Group Selecting Sample and hold A-D control register 2 [Address 03D4 ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 A-D control register 1 [Address 03D7 A-D control register 0 ADCON1 [Address 03D6...
Page 259: Repeat-Sweep Mode 0
A-D Converter M30240 Group 2.6.2.5 Repeat-sweep mode 0 In repeat-sweep 0 mode, select functions from those listed in Table 2.31 . An example using the indicated options is described below. Figure 2.87 shows the timing chart, and Figure 2.88 shows the set- up procedure.
Page 260 A-D Converter M30240 Group Selecting Sample and hold A-D control register 2 [Address 03D4 0 0 0 ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 A-D control register 1 [Address 03D7 A-D control register 0 ADCON1 [Address 03D6...
Page 261: Repeat-Sweep Mode 1
A-D Converter M30240 Group 2.6.2.6 Repeat-sweep mode 1 In repeat-sweep mode 1 select functions from those listed in Table 2.32 . An example using the indicated options is described below. Figure 2.90 shows the timing chart, and Figure 2.91 shows the set-up procedure Table 2.32: Operation of A-D converter in repeat-sweep mode 1 functions...
Page 262 A-D Converter M30240 Group Selecting Sample and Hold A-D control register 2 [Address 03D4 0 0 0 ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 A-D control register 1 [Address 03D7 A-D control register 0 ADCON1 [Address 03D6...
Page 263: Precautions
A-D Converter M30240 Group 2.6.3 Precautions Connect a capacitor between: the Vref pin and the AVss pin; AVcc pin and AVss pin; and each analog input pin and AVss pin. • Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
Page 264: A-D Converter Methods
A-D Converter M30240 Group 2.6.4 A-D Converter Methods 2.6.4.1 A/D Conversion method. 10-bit mode The A-D converter compares the reference voltage (V ) generated internally based on the contents of the successive comparison register with the analog input voltage (V ) input from the analog input pin.
Page 265 A-D Converter M30240 Group Table 2.34: Variation of successive comparison register and V while A-D conversion is in progress (10-bit mode) Successive approximation register change A-D converter stopped 1 0 0 0 0 0 0 0 0 0 1st comparison 1 0 0 0 0 0 0 0 0 0 2048 n9=1 + V...
Page 266: A/D Conversion Method, 8-Bit Mode
A-D Converter M30240 Group 2.6.4.2 A/D Conversion method, 8-bit mode In 8-bit mode, the 8 higher-order bits of the 10-bit successive comparison register becomes the A-D conversion result. Hence, if compared to a result obtained by using an 8-bit A-D converter, the voltage compared is different by 3 Vref/2048 (see underscored in Table 2.33), and differences in stepping points of output codes occur as shown in Figure 2.94.
Page 267 A-D Converter M30240 Group Table 2.36: Variation of successive comparison register and Vref while A-D converter is in progress Successive approximation register change A-D converter stopped 1 0 0 0 0 0 0 0 0 0 1st comparison 1 0 0 0 0 0 0 0 0 0 2048 n9=1 + V 1 0 0 0 0 0 0 0 0...
Page 268: A-D Converter Errors
A-D Converter M30240 Group 2.6.5 A-D Converter Errors 2.6.5.1 Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A-D conversion characteristics, and actual A-D conversion result. When measuring absolute accuracy, the voltage at the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A-D conversion characteristics, is used as an analog input voltage.
Page 269: Differential Non-Linearity Error
A-D Converter M30240 Group 2.6.5.2 Differential non-linearity error Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical A- D conversion characteristics (an analog input width that can meet the expectation of outputting an equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal code). If 10-bit resolution is used and if V (reference voltage) = 5.12 V, “differential non-linearity error = ±...
Page 270: Internal Equivalent Circuit
A-D Converter M30240 Group 2.6.6 Internal Equivalent Circuit Figure 2.98 shows the internal equivalent circuit of analog input. Vcc Vss AVcc Parasitic ON resistor diode ON resistor approx. 0.6kΩ Wiring resistor approx. 2kΩ C = Approx. 3.0pF approx. 0.2kΩ Analog input voltage ON resistor, Parasitic approx.
Page 271: Sensor Output Impedance
A-D Converter M30240 Group 2.6.7 Sensor Output Impedance To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 2.99 has to be completed within a specified period of time. With T as the specified time, time T is the time that switches SW2 and SW3 are connected to O in Figure 2.98.
Page 272 A-D Converter M30240 Group Table 2.37: Output impedance values based on the LSB values in 10-bit mode µ µ Resolution R0 max ) (MHz) R (kohm) C (pF) Cycle ( (LSB) (kohm) 0.25 (3 cycle, sample and 0.083 hold bit is enabled) -1.7 -0.8...
Page 273: Dmac
DMAC M30240 Group 2.7 DMAC 2.7.1 Overview The DMAC (Direct Memory Access Controller) transfers one data item held in the source address to the destination address every time a transfer request is generated. This transfer is done without using the CPU.
Page 274 DMAC M30240 Group 2.7.1.7 Switching functions (a) Switching between one-shot transfer and repeated transfer One-shot transfer refers to a mode in which the DMA is disabled after the transfer counter underflows. Repeated transfer refers to a mode in which a reload is carried out after the transfer counter under- flows.
Page 275 DMAC M30240 Group DMA0 request cause select register Symbol Address When reset DM0SL 03B8 Bit name Function Bit symbol DSEL0 b3 b2 b1 b0 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 DSEL1...
Page 276 DMAC M30240 Group DMAi control register DMAi control register Symbol Symbol Address Address When reset When reset DMiCON(i=0,1) DMiCON(i=0,1) 002C 002C , 003C , 003C 00000X00 00000X00 Bit symbol Bit symbol Bit name Bit name Function Function Transfer unit bit select bit Transfer unit bit select bit 0 : 16 bits 0 : 16 bits...
Page 277: Operation
DMAC M30240 Group 2.7.2 Operation 2.7.2.1 One-shot transfer mode In one-shot transfer mode, select functions from the items shown in Table 2.37. An example using the indicated options is described below. Figure 2.103 shows an example of operation and Figure 2.104 shows the set-up procedure.
Page 278 DMAC M30240 Group Setting DMAi request cause select register DMAi request cause select register (i = 0, 1) [Address 03B8 , 03BA DMiSL(i = 0, 1) DMA request cause select bit b3 b2 b1 b0 0 0 0 1 : Software trigger Software DMA request bit Set to “0”...
Page 279: Repeat Transfer Mode
DMAC M30240 Group 2.7.2.2 Repeat transfer mode In repeat transfer mode, an example of selected functions are shown in Table 2.38. Figure 2.105 shows an example of operation and Figure 2.106 shows the set-up procedure. Table 2.40: DMAC in repeated transfer mode functions Item Set-up From any SFR, ROM or RAM address to a fixed address...
Page 280 DMAC M30240 Group Setting DMAi request cause select register DMAi request cause select register (i = 0, 1) [Address 03B8 , 03BA DMiSL(i = 0, 1) DMA request cause select bit b3 b2 b1 b0 0 0 0 1 : Software trigger Software DMA request bit Set to “0”...
Page 281: Crc Calculation Circuit
CRC Calculation Circuit M30240 Group 2.8 CRC Calculation Circuit 2.8.1 Overview The Cyclic Redundancy Check (CRC) calculation circuit is used to detect errors in data blocks. The calculation method compares CRC code formed from transmission data by use of a polynomial generator with CRC check data to detect errors in transmission data.
Page 282 CRC Calculation Circuit M30240 Group CRC data register CRCD (1) Setting 0000 [03BD , 03BC CRC input register CRCIN (2) Setting 01 [03BE 2 cycles After CRC calculation is complete CRC data register CRCD 1189 [03BD , 03BC Stores CRC code The code resulting from sending 01 in LSB first mode is (1000 0000).
Page 283: Watchdog Timer
Watchdog Timer M30240 Group 2.9 Watchdog Timer 2.9.1 Overview The Watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an overview of the Watchdog timer. 2.9.1.1 Start procedure After reset, the Watchdog timer is stopped. Writing to the Watchdog timer start register initializes the Watchdog timer to 7FFF and causes it to start performing a down count.
Page 284: Related Registers
Watchdog Timer M30240 Group 2.9.1.6 Related Registers Figure 2.110 shows the memory map of Watchdog timer-related registers, and Figure 2.111 shows the Watchdog timer-related registers. 000E Watchdog timer start register (WDTS) 000F Watchdog timer control register (WDC) Figure 2.110: Memory map of Watchdog timer related registers Watchdog timer control register Address When reset...
Page 285: Operation
Watchdog Timer M30240 Group 2.9.2 Operation The following describes the operation of the Watchdog timer. Figure 2.112 shows the operation timing, and Figure 2.113 shows the set-up procedure. (1) Writing to the Watchdog timer start register initializes the Watchdog timer to 7FFF and causes it to start a down count.
Page 286: Address Match Interrupt
Address Match Interrupt M30240 Group 2.10 Address Match Interrupt 2.10.1 Overview The address match interrupt can be used for simplified debugging. Two address match interrupts can be set. The following is an overview of the address match interrupt. 2.10.1.1 Enable/Disable The address match interrupt enable bit can be used to enable and disable an address match interrupt.
Page 287: Related Registers
Address Match Interrupt M30240 Group 2.10.1.5 Related registers Figure 2.115 shows the memory map of address match interrupt-related registers, and Figure 2.116 shows address match interrupt-related registers. 0009 Address match interrupt enable register (AIER) 000A 000B 000C 000D 000E 000F 0010 0011 Address match interrupt register 0 (RMAD0)
Page 288: Operation
Address Match Interrupt M30240 Group 2.10.2 Operation This section describes an example of the address match interrupt operation. Figure 2.117 shows the set-up procedure of the address match interrupt, and Figure 2.118 shows an overview of the address match interrupt handling routine. (1) The address match interrupt handling routine sets an address to be used to cause the address match interrupt register to generate an interrupt.
Page 289: Key-Input Interrupt
Key-Input Interrupt M30240 Group 2.11 Key-Input Interrupt 2.11.1 Overview A Key-input interrupt occurs when a falling edge is input to any pin of Ports P0 or P1. The following is an overview of the key-input interrupt: 2.11.1.1 Enable/Disable The key-input interrupt can be enabled and disabled using the key-input interrupt register. The key-input interrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I flag).
Page 290 Key-Input Interrupt M30240 Group Interrupt control register (Note 2) When reset Address Symbol XXXX0000 004D KUPIC Bit symbol Bit name Function Interrupt priority level ILVL0 b2 b1 b0 select bit 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 ILVL1 0 1 1 : Level 3...
Page 291: Operation
Key-Input Interrupt M30240 Group 2.11.2 Operation This section describes an example of the Key-input interrupt operation. Figure 2.121 shows an example of a circuit that uses the key-input interrupt. Figure 2.122 shows an example of the timing operation for the Key-input interrupt. Figure 2.123 shows the set-up procedure for the Key-input interrupt. (1) Set the direction register of the ports to be changed to key-input interrupt pins to input, and set the pull-up function.
Page 292 Key-Input Interrupt M30240 Group Setting port Pi direction register Port Pi direction register [Address 03E2 , 03E3 PDi (i = 0,1) 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Setting pull-up control register 0 Pull-up control register 0 [Address 03FC PUR0 P0 0 to P0 3...
Page 293: Power Control
Power Control M30240 Group 2.12 Power Control 2.12.1 Overview ‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators, or decreasing the operation clock. The following is a description of the three available power control modes: 2.12.1.1 Modes Power control is available in three modes.
Page 294 Power Control M30240 Group priority level (IPL), and enable the interrupt enable flag (I flag). When an interrupt clears a mode, that interrupt is processed. Table 2.40 shows the interrupts that can be used for clearing stop mode and wait mode.
Page 295: Related Registers
Power Control M30240 Group sequence. When an interrupt is generated in stop mode, CM10 becomes “0” and stop mode is cleared. Starting oscillation and supplying Internal clock Φ executes the interrupt sequence as follows: In the interrupt sequence, the processor carries out the following in the sequence given: (a) The CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 .
Page 296 Power Control M30240 Group System clock control register 0 (Note 1) Symbol Address When reset 0 0 1 0006 Bit symbol Bit name Function b1 b0 0 0 : I/O port P3 CM00 Clock output function 0 1 : Invalid select bit 1 0 : f output...
Page 297: Stop Mode Set-Up
Power Control M30240 Group 2.12.2 Stop Mode Set-Up Settings and operation for entering stop mode are described here. (1) Enable the interrupt that is to be used for returning from stop mode. (2) Set the interrupt enable flag (I flag) to “1”. (3) Clear the protection register (4) Set all the clock stop bits to “1”.
Page 298: Wait Mode Set-Up
Power Control M30240 Group 2.12.3 Wait Mode Set-Up Settings and operation for entering wait mode are described here. (1) Enable the interrupt used that is to be used for returning from wait mode. (2) Set the interrupt enable flag (I flag) to “1”. (3) Clear the protection register.
Page 299: Precautions
Power Control M30240 Group 2.12.4 Precautions (1) The processor does not switch to stop mode when the NMI pin is at “L” level. (2) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized.
Page 300: Programmable I/O Ports
Programmable I/O Ports M30240 Group 2.13 Programmable I/O Ports 2.13.1 Overview Sixty-three programmable I/O ports and one input-only port are available. I/O pins also serve as I/O pins for built-in peripheral functions. Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In addition, each port has a pull-up control register that defines pull-up resistance in terms of 4 bits.
Page 301 Programmable I/O Ports M30240 Group 2.13.1.6 I/O functions of built-in peripheral devices Table 2.41 shows the relationship between ports and I/O functions of built-in peripheral devices. Table 2.43: Port and I/O function relationshipsPort and I/O function relationships Port Internal peripheral device I/O pins P0 to P1 Key input interrupt function input pins LED driver pins...
Page 302: Related Registers
Programmable I/O Ports M30240 Group 2.13.1.8 Related registers Figure 2.130 shows the memory map of programmable I/O ports-related registers, and Figures 2.131 to 2.134 show programmable I/O ports-related registers. 03E0 Port P0 (P0) 03E1 Port P1 (P1) 03E2 Port P0 direction register (PD0) 03E3 Port P1 direction register (PD1) 03E4...
Page 303 Programmable I/O Ports M30240 Group Port Pi register Symbol Address When reset Pi (i = 0 to 3, 6, 7, 10) 03E0 , 03E1 , 03E4 , 03E5 Indeterminate 03EC , 03ED , 03F4 Indeterminate Bit symbol Bit name Function Pi_0 Port Pi register...
Page 304 Programmable I/O Ports M30240 Group Port 2 Drive Capacity Register Symbol Address When reset P2DR 03FA Bit symbol Bit name Function P2DR0 LED drive capacity The N-channel high-drive capacity P2DR1 LED drive capacity is activated for the corresponding bit. P2DR2 LED drive capacity P2DR3 LED drive capacity...
Page 305 Chapter 3 Universal Serial Bus...
Page 306: Frequency Synthesizer
Frequency Synthesizer M30240 Group 3.1 Frequency Synthesizer This section explains how to setup the frequency synthesizer for USB operation. 3.1.1 Outline The frequency synthesizer generates the 48MHz clock that is necessary for the USB block and the f clock. These clocks are a multiple of the external input standard clock f(X ).
Page 307 Frequency Synthesizer M30240 Group Frequency Synthesizer Clock Control Register Symbol Address When reset O O O O O O O FSCCR 03DB Bit Symbol Bit Name Function 0 : Xin FSCCR0 Clock source selection 1 : fsyn Must always be set to "0" Reserved Figure 3.2: Frequency Synthesizer Clock Control Register (FSCCR)
Page 308: Operation
Frequency Synthesizer M30240 Group Frequency Synthesizer Multiply Register Symbol Address W hen reset 03DD Bit Symbol Bit Name Function Generates f by multiplying f Frequency Synthesizer X 2(n + 1) Multiplier Value n: FSM value Figure 3.5: Frequency Synthesizer Multiply Register (FSM) Frequency Synthesizer Divide Register Symbol Address...
Page 309: Prescaler
Frequency Synthesizer M30240 Group (5) After waiting the time required for supplying approximately 3.3V to the EXTCAP terminal, the USB µ clock enable bit should be set to “1.” The wait time then is (C+1)ms (the C is the capacity ( F) of the condenser that is connected to the EXTCAP terminal).
Page 310: Frequency Divider
Frequency Synthesizer M30240 Group 3.1.4.5 Frequency Divider Clock f is a divided down version of f . fsyn is generated via the Frequency Synthesizer Divide register (FSD). When the Frequency Synthesizer Divider register is set to 255, division is disabled and .
Page 311: Universal Serial Bus
Universal Serial Bus M30240 Group 3.2 Universal Serial Bus 3.2.1 Outline The Universal Serial Bus (USB) has the following features: • Complete USB Specification (version 1.1) Compatibility • Error-handling capabilities • FIFOs: • Endpoint 0: IN/OUT 32-byte • Endpoint 1: IN 128-byte OUT 128-byte •...
Page 312: Usb Related Registers
Universal Serial Bus M30240 Group 3.2.2 USB Related Registers Table 3.5 shows the memory location diagram for USB related registers. Table 3.5: USB-Related Registers Memory Location Diagram Address Register Name Acronym 000C USB Control Register USBC 001F USB Attach/Detach Register USBAD 0044 Suspend Interrupt Control Register...
Page 313: Usb Control Register
Universal Serial Bus M30240 Group 0328 USB Reserved 0329 USB Endpoint 3 IN Control / Status Register EP3ICS 032A USB Endpoint 3 OUT Control / Status Register EP3OCS 032B USB Endpoint 3 IN Maximum Packet Register EP3IMP 032C USB Endpoint 3 OUT Maximum Packet Register EP3OMP 032D USB Endpoint 3 OUT Write Count Register...
Page 314: Usb Attach/Detach Register
Universal Serial Bus M30240 Group USB Control Register Symbol Address When reset O O O USBC 000C Bit Symbol Bit Name Function Reserved Must always be set to "0" Tranceiver voltage converter 0: High current mode (Note 1) USBC3 High/Low current mode selection 1: Low current mode (Note 2) USB Tranceiver voltage converter 0: Disabled...
Page 315: Usb Address Register
Universal Serial Bus M30240 Group 3.2.2.3 USB Address Register This register holds the seven-bit USB address that is assigned from the host CPU. The USB function control unit uses the value of this register to decode USB token packet addresses. Before the device is configured at reset, the value is 00 Figure 3.9 shows the structure of the USB address register.
Page 316: Usb Interrupt Status Registers
Universal Serial Bus M30240 Group 3.2.2.5 USB Interrupt Status Registers These registers are used to determine the condition that caused a USB function interrupt, and to indi- cate a USB Reset, Suspend and Resume interrupt. When an interrupt request occurs, the correspond- ing status flag is set to “1”.
Page 317: Usb Interrupt Enable Registers
Universal Serial Bus M30240 Group 3.2.2.6 USB Interrupt Enable Registers The USB Interrupt Enable registers are used to enable or disable each of the interrupts that can gen- eral a USB function interrupt. At reset, all of the USB function interrupt status conditions are enabled. Figure 3.12 shows the structures of the Interrupt Enable Registers 1 and 2.
Page 318: Usb Frame Number Registers
Universal Serial Bus M30240 Group 3.2.2.7 USB Frame Number Registers These two registers hold the frame number (11 bits) received from the host CPU. They are read only. Figure 3.13 shows the structures of the USB frame number registers. USB Frame Number Low Register Symbol Address When reset...
Page 319: Usb Dmax Request Registers
Universal Serial Bus M30240 Group 3.2.2.9 USB DMAx Request Registers The USB DMAx Request Registers are used to select the endpoint used when USB is selected as the DMA0 or DMA1 request source. Any read or write request on endpoints 1-4 can be selected as the USB request source for a DMA transfer.
Page 320: Usb Endpoint Enable Register
Universal Serial Bus M30240 Group 3.2.2.10 USB Endpoint Enable Register Figure 3.16 The USB Endpoint Enable Register, shown in , is used to enable/disable an individual endpoint. End- point 0 is always enabled and cannot be disabled by firmware. All endpoints are enabled after reset. USB Endpoint Enable Register Symbol Address...
Page 321 Universal Serial Bus M30240 Group • Receive an illegal data toggle during a STATUS stage, • Receive an illegal data toggle during a SETUP stage, • Host requests more data than specified during the SETUP stage (receive an IN token when the DATA_END is set), •...
Page 322: Usb Endpoint 0 Maxp Register
Universal Serial Bus M30240 Group 3.2.2.12 USB Endpoint 0 MaxP Register The USB Endpoint 0 MaxP Register indicates the Maximum Packet size (MaxP) of Endpoint 0 (IN/ OUT). This register should be updated when the transmission of the SET_DESCRIPTOR command is received from the host CPU.
Page 323 Universal Serial Bus M30240 Group • UNDER_RUN Flag This bit is used for isochronous transfers only.The USB FCU sets this bit to “1” when a FIFO underrun is detected. When interrupts are enabled, a USB overrun/underrun interrupt occurs. Write a “0” to clear this bit.
Page 324: Usb Endpoint X In Maxp Register
Universal Serial Bus M30240 Group USB Endpoint x IN Control and Status Register Address Symbol When reset 0319 , 0321 EPxICS (x=1-4) 0329 , 0331 Bit Symbol Bit Name Function 0: Not ready INxCSR0 IN_PKT_RDY Flag 1: Ready Note 1 0: No FIFO underrun INxCSR1 UNDER_RUN Flag...
Page 325 Universal Serial Bus M30240 Group • OVER_RUN Flag This bit is used during isochronous transfers only. The USB Function Control Unit sets this bit to “1” when a FIFO overrun is detected. When interrupts are enabled, a USB overrun/underrun interrupt occurs. Write a “0” to clear this bit. •...
Page 326: Usb Endpoint X Out Maxp Register
Universal Serial Bus M30240 Group USB Endpoint x OUT Control and Status Register (Note 3) Symbol Address When reset EPiOCS (i=1-4) 031A , 0322 , 032A , 0332 Bit Symbol Bit Name Function 0: Not ready OUTxCSR0 OUT_PKT_RDY Flag 1: Ready Note 1 0: No FIFO OVerrun OUTxCSR1...
Page 327: Usb Endpoint X(X = 0 - 4) Fifo Register
Universal Serial Bus M30240 Group 3.2.2.19 USB Endpoint x(x = 0- 4) FIFO Register This is the USB IN (transmission) FIFO and USB OUT (receive) FIFO data register. Data should be written to this register at the time of transmission. Data should be read from this register at time of receipt.
Page 328: Transmission Precautions
Universal Serial Bus M30240 Group 3.2.3.1 Transmission Precautions The number of data packets in the IN FIFO should be determined from the IN_PKT_RDY bit and the TX_NOT_EPT flag. If there are two data packets in the IN FIFO (double buffer mode), the IN_PKT_RDY bit is cleared to “0”...
Page 329: Usb Isochronous Transfer
Universal Serial Bus M30240 Group 3.2.5 USB Isochronous Transfer Endpoints 1-4 can be used for isochronous transfers. The ISO bit of the USB Endpoint x (x=1-4) IN Control and Status register (INxCSR) and the ISO bit of the USB endpoint x (x=1-4) OUT control/status register (OUTxCSR) should both be set to “1”...
Page 330: Usb Reset Interrupt
Universal Serial Bus M30240 Group 0.0.0.0.1 Endpoint x IN Interrupt and Endpoint x OUT Interrupt When any USB Endpoint x IN interrupt status flags or USB Endpoint x OUT interrupt status flags of the USB interrupt status register 1 (USBIS1) and the USB interrupt status register 2 (USBIS2) are set to “1,”...
Page 331: Suspend Signal Interrupt
Universal Serial Bus M30240 Group 3.2.7.4 Suspend Signal Interrupt An interrupt request occurs when the interrupt status flag of the USB Suspend Interrupt Status register (SUSPIC) is “1.” The USB Suspend Interrupt Status flag is set to “1” when the USB Suspend signal is received (when there is no activity for at least 3ms on the D+/D- line).
Page 332 Universal Serial Bus M30240 Group Clearing the Protect Register Protect Register Address 0 0 1 PRCR 000A Write enable bit for system clock control registers 0 and 1 and frequency related registers 1 : Write enable Write enable bit for Processor Mode Register 0 and 1 0 : Write disabled Reserved bit Setting Frequency Synthesizer Related Registers...
Page 333 Universal Serial Bus M30240 Group Continued from previous page 2ms wait Check Frequency synthesizer locked state bit Selecting the Attach/Detach Register USB Attach/Detach Register Address 0 0 0 USBAD 001F Port P8 Control Bit 0 : Standard 1 : Use Port 8 as the curent supply termial to D+ Attach/Detach Selection Bit 0 : Detach...
Page 334 Universal Serial Bus M30240 Group Continued from previous page Endpoint 0 Control Transfer USB Endpoint 0 MAXP Register Address 0313 EP0MP to 3F Endpoint 1 - 4 (Bulk, Interrupt, and Isochronous transfers) Initialization USB Endpoint x IN MAXP Address EPiIMP (i = 1-4) 031B , 0323 , 032B...
Page 335: Usb Control Transfers And Set-Address Request
Universal Serial Bus M30240 Group C o n tin u e d fro m p re vio u s p a g e W h e n a n Iso ch ro n o u s T ra n sfe r is u se d : S e le ctin g th e U S B IS O C o n tro l R e g iste r U S B IS O C o n tro l R e g iste r A d d re s s...
Page 336 Universal Serial Bus M30240 Group A d d re sss A cq u isitio n P ro ce ssin g R o u tin e C onfirm ing R eceived D ata U S B E ndpoin t 0 C ontrol an d S tatus R egister A ddress E P 0 C S 03 11...
Page 337: Usb Transmission (In)
Universal Serial Bus M30240 Group 3.2.10 USB Transmission (IN) Figure 3.32 shows the procedures for Endpoints 1-4 USB IN transmission. Use caution when using isochronous transfer and the UNDER_RUN is “1” because a USB Endpoint x IN interrupt will occur. USB Endpoint x IN Interrupt Processing Routine Register Evacuation Process Confirm Data Transmission in FIFO...
Page 338: Usb Receive (Out)
Universal Serial Bus M30240 Group 3.2.11 USB Receive (OUT) The procedures for Endpoint 1-4 USB OUT transmission are shown in Figure 3.33 If isochronous transfer is used, it is necessary to be aware that a USB Endpoint x OUT interrupt occurs even when OVER_RUN is “1.
Page 339: Usb Suspend Interrupt
Universal Serial Bus M30240 Group 3.2.12 USB Suspend Interrupt In the event that a suspend signal is received from the host CPU, the USB function control unit sets the interrupt status flag of the USB Suspend Interrupt Status register (SUSPIC) and the USB suspend signal detection flag of the USB power processing register (USBPM) to “1.”...
Page 340 Universal Serial Bus M30240 Group Suspend Interrupt Processing Routine Setting the USB Control Register USB Control Register Address USBC 000C USB Transceiver Voltage Converter Current Mode Selection bit 1 : Low current mode USB Clock Enable Bit 0 : Disable 48 MHz Clock Supply Note: After setting bit 3, bit 5 should be established after waiting one cycle of the Φ.
Page 341 Universal Serial Bus M30240 Group Continued from previous page Set the Interrupt enable flag i = 1 Stop all Clocks System Clock Control Register Address 0 0 1 0007 All clock stop control bit 0 : Clocks on 1 : All clocks off (stop mode) Note: After setting bit 3, bit 5 should be established after waiting one cycle of the Φ.
Page 342: Usb Resume Interrupt
Universal Serial Bus M30240 Group 3.2.13 USB Resume Interrupt If a resume signal is received from the host CPU while in the suspend mode, the USB Function Control unit sets the USB Resume Signal Interrupt Status Flag of the USB Interrupt Status Register 2 (USBIS2) and the USB Resume Signal Detection Flag of the USB Power Processing Register (USBPM) to “1”.
Page 343 Universal Serial Bus M30240 Group Continued from previous page Checking the Frequency Synthesizer Locked State Bit Frequency Synthesizer Control Register Address 1 0 0 03DC Frequency Synthesizer Locked State Bit 0 : Unlocked State (Note) 1 : Locked (Frequency Synthesizer Stable) Note: Recheck after waiting 0.1 ms until it becomes "1".
Page 344: Usb Precautions
Universal Serial Bus M30240 Group 3.2.14 USB Precautions • When the USB Reset Interrupt Status flag is set to “1”, the contents in the USB internal registers (addresses 0300 -0335 ) will return to their reset values. However, the following register are not affected by a USB reset: •...
Page 345 Universal Serial Bus M30240 Group • Example of USB Function Interrupt C Language ram1=USBIS1; /*Read from USB Interrupt Status register 1*/ ram2=USBIS2; /*Read from USB Interrupt Status register 2*/ ram2 &=0x1F; /*Mask flags except USB Function Interrupt status flags*/ USBIS1=ram1; /*Write to USB Interrupt Status register 1*/ USBIS2=ram2;...
Page 346 Universal Serial Bus M30240 Group Rev.1.00 Sep 24, 2003 Page 328 of 360...
Page 347: Chapter 4: Interrupts
Chapter 4 Interrupts...
Page 348: Overview Of Interrupts
Overview of Interrupts M30240 Group 4.1 Overview of Interrupts 4.1.1 Type of Interrupts Figure 4.1 lists the types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction INT instruction Interrupt Reset Special Watchdog timer Hardware Single step Address match Peripheral I/O (Note) Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Page 349: Hardware Interrupts
Overview of Interrupts M30240 Group The stack pointer (SP), used for the INT interrupt, is dependent on which software interrupt number is involved. When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack pointer (ISP).
Page 350: Interrupt Vector Tables
Overview of Interrupts M30240 Group • A-D conversion interrupt This is an interrupt that the A-D converter generates. • UART0, UART1 and UART2 transmission interrupt These are interrupts that the serial I/O transmission generates. • UART0, UART1 and UART2 reception interrupt These are interrupts that the serial I/O reception generates.
Page 351: Variable Vector Tables
Overview of Interrupts M30240 Group 4.1.2.2 Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB indicates becomes the area for the variable vector tables.
Page 352: Interrupt Control
Overview of Interrupts M30240 Group 4.1.3 Interrupt Control Table 4.3 shows the memory map of the interrupt control registers, and Figure 4.2 shows the interrupt control registers. Table 4.3: Memory map of the interrupt control registers Address Register name Acronym 0044 USB Suspend Interrupt Control register SUSPIC...
Page 353 Overview of Interrupts M30240 Group Symbol Address When reset Interrupt control register SUSPIC 0044 XXXXX000 RSMIC 0046 XXXXX000 BCNIC 004A XXXXX000 DMiIC(i=0, 1) 004B , 004C XXXXX000 KUPIC 004D XXXXX000 ADIC 004E XXXXX000 SiTIC(i=0 to 2) 0051 , 0053 , 004F XXXXX000 SiRIC(i=0 to 2) 0052...
Page 354: Interrupt Request Bit
Overview of Interrupts M30240 Group 4.1.3.1 Interrupt Request Bit The interrupt request bit is located in the interrupt control register of each interrupt. It is set to “1” by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the correspond- ing interrupt vector, the request bit is set to “0”...
Page 355 Overview of Interrupts M30240 Group The following are conditions under which an interrupt is accepted: • interrupt enable flag (I flag) = 1 • interrupt request bit = 1 • interrupt priority level > IPL Table 4.4: Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Priority order...
Page 356: Interrupt Priority
Overview of Interrupts M30240 Group 4.1.3.4 Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (check- ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit.
Page 357: Ipl Variation
Overview of Interrupts M30240 Group 4.1.3.5 IPL Variation If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 4.6 is set in the IPL.
Page 358: Interrupt Sequence
Overview of Interrupts M30240 Group 4.1.4 Interrupt Sequence An interrupt sequence is performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence at the next cycle.
Page 359 Overview of Interrupts M30240 Group Stack area Stack area Address Address [SP] m – 4 New stack m – 4 Program counter (PC pointer value m – 3 m – 3 Program counter (PC m – 2 m – 2 Flag register (FLG Flag register Program...
Page 360 Overview of Interrupts M30240 Group 4.1.4.2 Interrupt Response Time Interrupt response time is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time includes the period from the oc- currence of an interrupt to the completion of the instruction under execution at that moment (a) and Figure 4.7 shows the interrupt response time.
Page 361 Overview of Interrupts M30240 Group 4.1.4.3 Interrupt Routine Return Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of the interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area.
Page 362 Overview of Interrupts M30240 Group Interrupt request Nesting generated Reset Main routine Time I = 0 IPL = 0 Interrupt 1 I = 1 Interrupt priority level = 3 Interrupt 1 I = 0 IPL = 3 Interrupt 2 Multiple interrupts I = 1 Interrupt priority level = 5 Interrupt 2...
Page 363 Overview of Interrupts M30240 Group 4.1.6 Precautions 4.1.6.1 Reading address 00000 • When a maskable interrupts occurs, the CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. • The interrupt request bit of the corresponding interrupt written in address 00000 is then set to “0”.
Page 364 Overview of Interrupts M30240 Group 4.1.6.5 The NMI interrupt • As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the Vcc pin if unused. • Do not get into stop mode or wait mode with the NMI pin set to “L”. 4.1.6.6 Rewrite the interrupt control register See section 4.1.3.6 Interrupt Control Rewrite for precautions on writing to the interrupt control regis- ters.
Page 365 Chapter 5 Built-in PROM Version...
Page 366 Built-in PROM Version M30240 Group 5.1 Built-in PROM Version The built-in PROM (programmable ROM) version has the same function as the mask ROM version. It is possible to program the built-in PROM with a general purpose PROM programmer by using a programming adapter that is suitable for the microcomputer.
Page 367 EPROM version M30240 Group Table 5.1: Pin functions in EPROM mode Input/ Name Functions Output , P3 , and P3 function as PGM, OE, and CE to P3 Control input Input respectively. Connect P3 to Vcc pin. to P3 Address input (A16 to A17) Input High order (A16 &...
Page 368 EPROM version M30240 Group 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 M30240ECFP 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Figure 5.1: Pin connections in EPROM mode (1) Rev.1.00 Sep 24, 2003 Page 350 of 360...
Page 369 EPROM version M30240 Group 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 M30240ECFS (Top View) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Figure 5.2: Pin connections in EPROM mode (2) Rev.1.00 Sep 24, 2003 Page 351 of 360...
Page 370 EPROM version M30240 Group 5.2.2 Input/Output signals 5.2.2.1 Read To read the built-in PROM, perform the following: • Set the CE and OE pins to “L” level • Set the PGM pin to “H” level • Input address (A0 to A16) of the data to be read, into the address input pins. The contents of the built-in PROM will now be output to the data I/O pins (D0 to D7).
Page 371 EPROM version M30240 Group Figure 5.3 shows the programming algorithm flow chart. START ADDR = FIRST LOCATION Vcc = 6.0 V Vpp = 12.5 V X = 0 PROGRAM ONE PULSE OF 0.2 ms X = X+1 X = 25? DEVICE VERIFY FAIL...
Page 372 EPROM version M30240 Group 5.2.3.1 Electrical Characteristics. AC Electrical characteristics (Ta = 25 ± 5°C, Vcc = 6 ± 0.25V, Vpp = 12.5 ± 0.3V unless Table 5.4: otherwise noted) Limits Measuring Symbol Parameter Unit Condition Min. Type Max. µ s Address setup time µ...
Page 373 Usage Precaution M30240 Group 5.3 Usage Precaution 5.3.1 Built-in PROM versions High voltage is required to program the built-in PROM. Do not apply excessive voltage. Use caution during power on. 5.3.2 One-time PROM versions Blank one-time PROM versions (M30240ECFP) are also shipped with those programmed by users. For these microcomputers, a programming test and screening are not preformed in the assembly process and subsequent processes.
Page 374 Usage Precaution M30240 Group Rev.1.00 Sep 24, 2003 Page 356 of 360...
Page 375 Chapter 6 Standard Characteristics...
Page 376 Standard DC Characteristics M30240 Group 6.1 Standard DC Characteristics The standard characteristics given in this section are examples of M30240EC. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”. = 5V Ta = 25 C Figure 6.1: IOL-VOL standard characteristics of port P0 to P10 (except P8 = 5V...
Page 377 Standard DC Characteristics M30240 Group Measurement conditions: Vcc = 5V, Ta = 25 C, f(Xin): square waveform input When access to ROM and RAM without wait, f(Xin) = 1MHz to 12 MHz Division ratio: f(Xin)/1 Register setting condition: Xin-Xout drive select bit = "1" (High) Vcc = 5V with USB ON with USB OFF...
Page 378 Standard DC Characteristics M30240 Group Rev.1.00 Sep 24, 2003 Page 360 of 360...
Page 379 REVISION HISTORY M30240 Group User’s Manual Rev. Date Description Page Summary 1.00 09/24/2003 First Edition Issued ( 1 / 1)
Page 380 M30245 Group User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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M30240 series M30240m5-fp series M30240m6-fp series M30240ecfp

Renesas M16C Series User Manual

Chapter 1: Hardware

Description

Operation of Functional Blocks

Usage Precautions

Specifications

Applications

Chapter 2: Peripheral Functions Usage

Protect

Timer a

Timer B

Clock-Synchronous Serial I/O

Clock-Asynchronous Serial I/O (UART)

A-D Converter

Dmac

CRC Calculation Circuit

Watchdog Timer

Address Match Interrupt

Key-Input Interrupt

Power Control

Programmable I/O Ports

Chapter 3 : Universal Serial Bus

Universal Serial Bus

Chapter 4: Interrupts

Overview of Interrupts

Quick Links

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Summary of Contents for Renesas M16C Series