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M16C/5L Group, M16C/56 Group
18.3
Operations
18.3.1
Base Timer
The base timer is a free-running counter which counts an internally generated count source.
Table 18.5 lists the specifications of the base timer, Figure 18.3 shows the block diagram of the base
timer, Table 18.6 lists the base timer associated registers and their settings, Figure 18.4 shows an
op era t io n exam ple with incre me nting, F ig ure 1 8.5 sh ows an op era t ion exa mp le with
incrementing/decrementing, and Figure 18.7 shows an operation example with two-phase pulse signal
processing.
Table 18.5
Base Timer Specifications
Item
Count source (fBT1)
Count operations
Count start condition
Count stop condition
Base timer reset conditions
Base timer reset value
Interrupt requests
Read from base timer
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
f1TIMS or f2TIMS divided by (n + 1), two-phase pulse clock divided by (n + 1)
n is a G1DV register setting value from 0 to 255.
However, when n is 0, there is no division.
•
Increment
•
Increment/decrement
•
Two-phase pulse signal processing
Set the BTS bit in the G1BCR1 register to 1 (base timer starts counting).
Set the BTS bit in the G1BCR1 register to 0 (base timer reset).
•
The base timer value matches the G1BTRR register value.
•
The base timer value matches the G1PO0 register value.
A low signal is input to the INT1 external interrupt pin.
•
•
The BTS bit in the G1BCR1 register is 0 (base timer reset).
0000h
•
Bit 14 or bit 15 in the G1BT register overflows.
•
The base timer value matches the G1BTRR register value.
•
The count value is returned when reading the G1BT register while the base timer
is counting.
•
An undefined value is returned when reading the G1BT register while the base
timer is being reset and the BTS bit is 0.
Specification
18. Timer S
Page 368 of 803
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