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M16C/5L Group, M16C/56 Group
Priority of peripheral
function interrupts
(if priority levels are
same)
Figure 12.8
Interrupt Priority Select Circuit
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Priority level of each interrupt
High
IC/OC channel 3
IC/OC channel 1, SCL/SDA
IC/OC channel 0
CAN0 transmit FIFO
CAN0 transmission complete
IC/OC base timer
IC/OC channel 2
2
IC/OC interrupt 1 (0 to 7), I
C-bus
IC/OC interrupt 0 (0 to 7)
CAN0 receive FIFO
Real-time clock cycle
UART3 transmit, CAN0 error
UART4 receive
DMA3
CAN0 reception complete
UART3 receive
CAN0 wake-up
UART4 transmit,
real-time clock compare
DMA2
INT1
Timer B2
Timer B0
Timer A3
Timer A1
INT3
INT2
INT0
Low
High
Priority of peripheral function interrupts (if priority levels are same)
IPL
I flag
Address match
Watchdog timer
Oscillator stop/restart detector
Voltage Monitor 2
DBC
NMI
Level 0
(initial value)
Priority level of each interrupt
Timer B1
Timer A4
Timer A2
UART1 receive
UART0 receive
UART2 receive, ACK2
A/D conversion
DMA1
UART2 bus collision, task monitor timer
Timer A0
UART1 transmit
UART0 transmit
UART2 transmit, NACK2
Key input interrupt
DMA0
12. Interrupts
INT5
INT4
Low
Interrupt request level determine output
To clock generating circuitry
Interrupt request
accepted
Page 190 of 803
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