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M16C/5L Group, M16C/56 Group
(1) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit in
the G1BCR0 register are all 0).
Base timer
OUTC1_ j pin
G1IRj bit
j = 0 to 7
m: G1POj register value
G1IRj: Bit in the G1IR register
The diagram above applies under the following conditions:
⋅ The IVL bit in the G1POCRj register is 0 (output low as default) and the INV bit is 0 (output is not inverted).
⋅ Bits IOj1 and IOj0 in registers G1IOR0 and G1IOR1 are 00b (outputs high or low depending on the mode selected by bits
MOD1 and MOD0 in the G1POCRj register).
⋅ The EOCj bit in the G1OER register is 0 (output enabled).
(2) When the base timer matches either of the following registers, the base timer is reset:
(a) G1PO0 register (when the RST1 bit is 1 and bits RST4 and RST2 are 0)
(b) G1BTRR register (when the RST4 bit is 1 and bits RST2 and RST1 are 0)
Base timer
OUTC1_ j pin
G1IRj bit
When (a), j = 1 to 7. When (b), j = 0 to 7.
m: G1POj register value
n: G1PO0 register or G1BTRR register setting value
G1IRj: Bit in the G1IR register
The above assumes the following:
⋅ The IVL bit in the G1POCRj register is 0 (output low as default) and the INV bit is 0 (output is not inverted).
⋅ Bits IOj1 and IOj0 in registers G1IOR0 and G1IOR1 are 00b (outputs high or low depending on the mode selected by bits
MOD1 and MOD0 in the G1POCRj register).
⋅ The EOCj bit in the G1OER register is 0 (output enabled).
Figure 18.14 Single-Phase Waveform Output Mode Operation (1/2)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
FFFFh
m
0000h
m
65536-m
fBT1
fBT1
Output high
65536
fBT1
FFFFh
n + 1
m
0000h
m
n + 2 - m
fBT1
fBT1
Output high
n + 2
fBT1
Output high
Output low
To set this bit to 0,
write 0 by a program
Output high
To set this bit to 0,
write 0 by a
program
18. Timer S
Output high
Output low
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