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M16C/5L Group, M16C/56 Group
(1) The rising edge is selected as a time measurement trigger (bits CTS1 and CTS0 in the
G1TMCRj register are 01b).
fBT1
Base timer
INPC1_ j pin input signals,
or trigger signals after
passing the digital filter
G1IRj bit
in the G1IR register
G1TMj register
j = 0 to 7
Note:
1. Input pulse applied to the INPC1_ j pin requires at least 1.5 fBT1 cycles for both high and low widths.
(2) Both the rising and falling edges are selected as a time measurement trigger (bits CTS1 and
CTS0 are 11b).
fBT1
Base timer
INPC1_ j pin input signals,
or trigger signals after
passing the digital filter
G1IRj bit
in the G1IR register
(1)
G1TMj register
j = 0 to 7
Notes:
1. When the G1IRj bit is 1 and a trigger signal is generated, the IC/OC interrupt 0 and IC/OC interrupt 1 requests are not
generated. However, values in the G1TMj register change.
2. Input pulse applied to the INPC1_j pin requires at least 2.5 fBT1 cycles for both the high and low widths.
(3) Trigger signal when the digital filter function is used (bits DF1 and DF0 in the G1TMCRj
register are 10b or 11b).
Sampling clock
INPC1_ j pin
Trigger signal after
passing the digital filter
j = 0 to 7
Figure 18.12 Time Measurement Function (2/2)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
n-2
n-1
n
n+1
n+2
n+3
Maximum delay of two fBT1 cycles
n
n-2
n-1
n
n+1
n+2
n+3
(Note 2)
n
Signals that do not match three
times are ignored.
n+4
n+5
n+6
n+7
n+8
n+9 n+10 n+11 n+12 n+13 n+14
(Note 1)
(Note 1)
n + 5
n+4
n+5
n+6
n+7
n+8
n+9 n+10 n+11 n+12 n+13 n+14
(Note 2)
n + 2
A trigger signal is delayed
by passing the digital filter
18. Timer S
To set this bit to 0, write 0
by a program
n + 8
To set this bit to 0,
write 0 by a program
n + 8
n + 12
Maximum 3.5 cycles of the
sampling clock
Page 378 of 803
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