Renesas M16C/50 Series User Manual page 522

M16C/5L Group, M16C/56 Group
21.3.4.1 Clock Phase Setting Function
One of four combinations of transmit/receive clock phases and polarities can be selected using the
CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register.
Make sure the transmit/receive clock polarity and phase are the same for the master and slaves to be
used for communication.
Figure 21.28 shows the Transmit and Receive Timing in Master Mode (Internal Clock).
Clock output
(CKPOL = 0, CKPH = 0)
Clock output
(CKPOL = 1, CKPH = 0)
Clock output
(CKPOL = 0, CKPH = 1)
Clock output
(CKPOL = 1, CKPH = 1)
Data output timing
Data input timing
CKPOL: Bit in the U2C0 register
CKPH: Bit in the U2SMR3 register
Figure 21.28 Transmit and Receive Timing in Master Mode (Internal Clock)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
High
Low
High
Low
High
Low
High
Low
High
D0 D1
Low
21. Serial Interface UARTi (i = 0 to 4)
D2 D3 D4 D5 D6 D7
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