Renesas M16C/50 Series User Manual page 591

M16C/5L Group, M16C/56 Group
23.1.2 CAN0 Clock Select Register (C0CLKR)
CAN0 Clock Select Register
b7 b6 b5 b4 b3 b2 b1
0 0 0 0
Notes:
1. Write to the CCLKS bit in CAN reset mode.
2. To set the CCLKS bit to 1, the frequency of the BCLK should be equal to or higher than the frequency of the
main clock.
Figure 23.3 C0CLKR Register
23.1.2.1 CCLKS Bit
When the CCLKS bit is set to 0, the CAN clock source (fCAN) originates from the PLL.
When this bit is set to 1, fCAN originates directly from the external XIN pin bypassing the PLL.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
C0CLKR
Bit Symbol
CAN Clock Source
CCLKS
Select Bit
—
Reserved
(b1)
—
No register bit; should be written with 0 and read as 0
(b2)
—
Reserved
(b3)
—
Reserved
(b4)
—
No register bits; If necessary, set to 0. The read value is 0.
(b6-b5)
—
Reserved
(b7)
Address
D7C7h
Bit Name
0: BCLK
(1)
1: Main clock
Set to 0.
Set to 0.
Should be written with 0 and read as
undefined value.
Set to 0.
23. CAN Module
Reset Value
00h
Function RW
RW
(2)
RW
—
RW
RW
—
RW
Page 554 of 803