Renesas M16C/50 Series User Manual page 228

M16C/5L Group, M16C/56 Group
12.7.9 Multiple Interrupts
The following shows the internal bit states when control has branched to an interrupt routine.
•
I flag = 0 (interrupt disabled)
•
IR bit = 0 (interrupt not requested)
•
Interrupt priority level = IPL
By setting the I flag to 1 (interrupt enabled) in the interrupt routine, an interrupt request with higher
priority than the IPL can be acknowledged.
The interrupt requests not acknowledged because of their low interrupt priority level are kept pending.
When the IPL is restored by an REIT instruction and interrupt priority is resolved against it, the pending
interrupt request is acknowledged if the following condition is met:
Interrupt priority level of pending interrupt request > Restored IPL
INT Interrupt
12.8
The INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected
using the IFSRi bit in the IFSR register.
To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to 1 ( INT4 ). To use the INT5 interrupt, set
the IFSR7 bit in the IFSR register to 1 ( INT5 ).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
12. Interrupts
Page 191 of 803