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M16C/5L Group, M16C/56 Group
13. Watchdog Timer
13.1
Introduction
The watchdog timer contains a 15-bit counter, and the count source protection mode can be
enabled/disabled.
Table 13.1 shows the watchdog timer specifications and Figure 13.1 shows a block diagram of the watchdog
timer. Refer to 6.4.7 "Watchdog Timer Reset" for details on the watchdog timer reset.
Table 13.1
Watchdog Timer Specifications
Item
Count Source Protection Mode Disabled
Count source
CPU clock
Count operation Decrements
One of the following is selectable: (Selected by the WDTON bit in the OFS1 address)
Count start
•
conditions
•
•
•
Count stop
•
conditions
•
Watchdog timer
•
counter refresh
timing
•
Watchdog timer
7FFFh
initial value
When
A watchdog timer interrupt is generated or
underflows
watchdog timer reset is initiated
•
Selectable
•
functions
•
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Counting starts automatically after reset.
Counting starts by a write to the WDTS register.
Stop mode
Wait mode
Software commands executed in EW1
mode, except when executing the
suspend function.
Resets (refer to 6. "Resets" for details)
Write 00h followed by FFh to the WDTR register.
Watchdog timer underflow
Prescaler divide ratio
Divide-by-16 or divide-by-128 (selected by the WDC7 bit in the WDC register)
However, divide-by-2 is selected when the CM07 bit in the CM0 register is 1 (sub
clock).
Count source protection mode
Enabled or disabled (selected by the CSPROINI bit in the OFS1 address and the
CSPRO bit in the CSPR register)
Watchdog timer refresh period
Selectable by setting bits WDTRCS1 and WDTRCS0 in the OFS2 address.
Count Source Protection Mode Enabled
Dedicated 125 kHz on-chip oscillator for
watchdog timer (fWDT)
None
Selectable by using bits WDTUFS1 and
WDTUFS0 in the OFS2 address
Watchdog timer reset is initiated
13. Watchdog Timer
Page 199 of 803
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