Renesas M16C/50 Series User Manual page 243

M16C/5L Group, M16C/56 Group
13.3.2 Optional Function Select Address 2 (OFS2)
Optional Function Select Address 2
b7 b6 b5 b4 b3 b2 b1
1 1 1 1
WDTUFS1 to WDTUFS0 (Watchdog Timer Initial Setting Bit) (b0-b1)
Enabled when CSPRO bit in the CSPR register is 1 (count source protection mode enabled).
WDTRCS1 to WDTRCS0 (Watchdog Timer Refresh Duty Cycle Setting Bit) (b3-b2)
Assuming the cycle of the watchdog timer underflow is 100%, bits WDTRCS1 and WDTRCS0 select
the refresh period for the watchdog timer.
Refer to 13.4.1 "Refresh Operation Period" for details.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0 Symbol
OFS2
Bit Symbol Bit Name
WDTUFS0
Watchdog timer initial setting bit
WDTUFS1
WDTRCS0
Watchdog timer refresh duty
cycle setting bit
WDTRCS1
—
Reserved bits
(b7-b4)
Address
FFFDBh
Function
b1 b0
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
Refresh period is the last n% of watchdog timer
period:
b3 b2
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
Set to 1.
13. Watchdog Timer
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