Download Print this page

Renesas M16C/50 Series User Manual page 813

Advertisement

M16C/5L Group, M16C/56 Group
28.11 Notes on Timer A
28.11.1 Common Notes on Multiple Modes
28.11.1.1 Register Setting
The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR,
TAi, TAi1, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, TCKDIVC0, PCLKR, and bits TAZIE,
TA0TGL, and TA0TGH in the ONSF register before setting the TAiS bit in the TABSR register to 1
(count started) (i = 0 to 4).
Set the TCDIV00 bit in the TCKDIVC0 register before setting other registers associated with timer A.
After changing the TCDIV00 bit, set other registers associated with timer A again.
Always make sure registers TAiMR, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS,
TCKDIVC0, PCLKR, and bits TAZIE, TA0TGL, TA0TGH in the ONSF register are modified while the
TAiS bit is 0 (count stopped), regardless of whether after reset or not.
28.11.1.2 Event or Trigger
When bits TAiTGH to TAiTGL in the registers ONSF or TRGSR are 01b, 10b, or 11b, an event or a
trigger occurs when an interrupt request of the selected timer is generated. An event or trigger occurs
while an interrupt is disabled because an interrupt request signal is generated regardless of the I flag,
IPL, or interrupt control registers.
For some modes of the timers selected using bits TAiTGH to TAiTGL, an interrupt request is
generated by a source other than overflow or underflow.
For example, when using pulse-period measurement mode or pulse-width measurement mode in
timer B2, an interrupt request is generated at an active edge of the measurement pulse. For details,
refer to the "Interrupt request generation timing" in each mode's specification table.
28.11.1.3 Influence of SD
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V/RXD1, P7_3/ CTS2 / RTS2 /TA1IN/ V /TXD1, P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/U/TSUDA, P8_1/TA4IN/ U /TSUDB
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
28. Usage Notes
Page 776 of 803

Advertisement

loading