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M16C/5L Group, M16C/56 Group
SDA2
Delay
circuit
ACKC = 1
Noise
filter
SCL2
IICM = 0
IICM = 1
Noise
filter
The above assumes the following: bits SMD2 to SMD0 in the U2MR register are 010b and the IICM bit in the U2SMR register is 1.
IICM: Bit in the U2SMR register
IICM2, SWC, ALS, SWC2, SDHI: Bits in the U2SMR2 register
STSPSEL, ACKD, ACKC: Bits in the U2SMR4 register
If the IICM bit is 1, the signal level on the pin can be read even when the port direction bit corresponding to the SCL2 pin is 1 (output mode).
Figure 21.13 I 2 C Mode Block Diagram
U2BRG count source
n: U2BRG register setting value
Figure 21.14 Internal Clock Configuration
Table 21.13
I/O Pin Functions in I
Pin Name
(1, 2)
SCL2
(1, 2)
SDA2
Note:
1.
Set the port direction bit sharing pin to 0.
Pins CLK2 and CTS2 / RTS2 are not used (they can be used as I/O ports).
2.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
STSPSEL = 1
STSPSEL = 0
ACKC = 0
SDHI
ALS
ACKD bit
D
Q
Arbitration
T
Start condition
detector
Stop condition
detector
Falling edge
detector
Port register
R
I/O port
Q
Internal clock
STSPSEL=0
SWC2
UART2
STSPSEL
External
= 1
clock
R
S
2
C Mode
I/O
I/O
I/O
Start and stop condition generation block
SDA (STSP)
SCL (STSP)
IICM2 = 1
Transmission
register
UART2
Reception
register
UART2
Bus
S
Q
busy
R
D
Q
T
D
Q
ACK
(1)
T
9th bit
CLK
control
UART2
8th bit falling edge
SWC
U2BRG
1/(n+1)
1/2
Function
Clock input or output
Data input or output
21. Serial Interface UARTi (i = 0 to 4)
DMA0 to DMA3 request
UART2 transmit, NACK
interrupt request
IICM = 1 and
IICM2 = 0
DMA0, DMA2 request
IICM2 = 1
UART2 receive,
ACK interrupt request,
DMA1, DMA3 request
IICM = 1 and
IICM2 = 0
NACK
Start/stop condition detection
interrupt request
SCL clock
(internal clock)
Sampling clock of
digital delay circuit
Page 468 of 803
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