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M16C/5L Group, M16C/56 Group
22. Multi-master I
22.1
Introduction
The multi-master I
data transmit/receive format, and is equipped with arbitration lost detect and clock synchronous functions.
Table 22.1 lists the Multi-master I
Detection Function, Figure 22.1 shows the Multi-master I
lists the I/O Ports.
Table 22.1
Multi-master I
Item
Formats
Communication modes
Bit rate
I/O pins
Interrupt request generating
sources
Selectable functions
2
fVIIC: I
C-bus system clock
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C-bus Interface
2
2
C-bus interface (I
C interface) is a serial communication circuit based on the I
2
C-bus Interface Specifications, Table 22.2 lists the I
2
C-bus Interface Specifications
2
Based on I
C-bus standard:
7-bit addressing format
Fast-mode
Standard clock mode
2
Based on I
C-bus standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kbps to 400 kbps (fVIIC = 4 MHz)
Serial data line SDAMM (SDA)
Serial clock line SCLMM (SCL)
2
•
I
C-bus interrupt
Completion of transmission
Completion of reception
Slave address match detection
General call detection
Stop condition detection
Timeout detection
•
SDA/SCL interrupt
Rising or falling edge of the signal of the SDAMM or SCLMM pin
2
•
I
C-bus interface pin input level select
Selectable input level with I
•
Timeout detection
A function that detects when the SCLMM pin is driven high over a certain
period of time when the bus is busy.
•
Free data format select
A function that generates an interrupt request when receiving the first byte
of data, regardless of the slave address value.
22. Multi-master I
2
C-bus Interface Block Diagram, and Table 22.3
Function
2
C-bus input level or SMBus input level
2
C-bus Interface
2
C-bus
2
C Interface
Page 499 of 803
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