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M16C/5L Group, M16C/56 Group
CRX0
CTX0
BCLK
Main clock
BRP: Bit in the C0BCR register
CCLKS: Bit in the C0CLKR register
fCANCLK: CAN communication clock
fCAN: CAN system clock
Figure 23.1
CAN Module Block Diagram
• CRX0/CTX0:
• Protocol controller:
• Message box:
• Acceptance filter:
• Timer:
• Wake-up function:
• Interrupt generator:
• CAN SFRs:
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Peripheral bus
CAN SFRs
Protocol
controller
ID priority transmit
fCANCLK
Baud rate
prescaler (BRP)
CCLKS
fCAN
CAN input/output pins
Handles CAN protocol processing such as bus arbitration, bit timing at
transmission and reception, stuffing, and error handling, etc.
Consists of 32 mailboxes which can be configured as either transmit
or receive mailboxes. Each mailbox has an individual ID, data length
code, a data field (8 bytes), and a time stamp.
Performs filtering of received messages. Registers C0MKR0 to
C0MKR7 are used for the filtering process.
Used for the time stamp function. The timer value when storing a
message into the mailbox is written as the time stamp value.
Generates a CAN0 wake-up interrupt request when a message is
detected on the CAN bus.
Generates the following five types of interrupts:
- CAN0 reception complete interrupt
- CAN0 transmission complete interrupt
- CAN0 receive FIFO interrupt
- CAN0 transmit FIFO interrupt
- CAN0 error interrupt
CAN-associated registers. Refer to 23.1 "CAN SFRs" for details.
Acceptance filter
Message box
controller
Timer
CAN0 wake-up interrupt
CAN0 reception complete interrupt
CAN0 transmission complete interrupt
Interrupt
CAN0 receive FIFO interrupt
generator
CAN0 transmit FIFO interrupt
CAN0 error interrupt
23. CAN Module
Page 548 of 803
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