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Renesas M16C FAMILY Hardware Manual

Renesas M16C FAMILY Hardware Manual

16-bit single-chip microcomputer
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REJ09B0062-0091Z
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Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 0.91
Revision date: Sep 08, 2003
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
R8C/11 Group
Hardware Manual
M16C FAMILY/R8C/Tiny SERIES
Preliminary
www.renesas.com

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  • Page 1 REJ09B0062-0091Z R8C/11 Group Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES Preliminary Before using this material, please visit our website to confirm that this is the most current document available. Rev. 0.91 Revision date: Sep 08, 2003 www.renesas.com...
  • Page 2 • The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.

  • Page 3: How To Use This Manual

    How to Use This Manual This hardware manual provides detailed information on features in the R8C/11 Group mi- crocomputer. Users are expected to have basic knowledge of electric circuits, logical circuits and micro- computer. Each register diagram contains bit functions with the following symbols and descriptions. XXX register Symbol Address...
  • Page 4 M16C Family Documents Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware specifications (pin assignments, Hardware Manual memory maps, specifications of peripheral func- tions, electrical characteristics, timing charts) Detailed description about instructions and mi- Software Manual crocomputer performance by each instruction •...

  • Page 5: Table Of Contents

    Table of Contents SFR Page Reference Chapter 1. Overview .............. 1 1.1 Applications ........................1 1.2 Performance Outline ...................... 2 1.3 Block Diagram ........................ 3 1.4 Product Information ....................... 4 1.5 Pin Assignments......................5 1.6 Pin Description ....................... 6 Chapter 2. Central Processing Unit (CPU) ......7 2.1 Data Registers (R0, R1, R2 and R3) ................
  • Page 6 5.4 Voltage Detection Circuit ..................... 20 5.4.1 Voltage Detection Interrupt ........................25 5.4.2 Get Out Of Stop Mode Due To The Voltage Detection Interrupt ............27 Chapter 6. Clock Generating Circuit........28 6.1 Main Clock ........................33 6.2 Ring Oscillator Clock ....................34 6.2.1 Low-speed Ring Oscillator ........................
  • Page 7 12.1.1 Timer Mode ............................73 12.1.2 Pulse Output Mode ..........................74 12.1.3 Event Counter Mode ........................... 75 12.1.4 Pulse Width Measurement Mode ....................... 76 12.1.5 Pulse Period Measurement Mode ..................... 78 12.2 Timer Y......................... 80 12.2.1 Timer Mode ............................83 12.2.2 Programmable Waveform Generation Mode ..................
  • Page 8 17.4.3 Software Commands ........................158 17.4.4 Status Register ..........................162 17.4.5 Full Status Check ..........................163 17.5 Standard Serial I/O Mode ..................165 17.5.1 ID Code Check Function ........................165 Chapter 18. On-chip Debugger ........169 18.1 Address Match Interrupt ..................169 18.2 Single Step Interrupt ....................
  • Page 9 SFR Page Reference Symbol Page Register Symbol Page Register Address Address 0040 0000 0041 0001 0042 0002 0043 0003 0044 Processor mode register 0 0004 0045 Processor mode register 1 0005 0046 System clock control register 0 0006 0047 0007 System clock control register 1 0048 0008...
  • Page 10 SFR Page Reference Symbol Page Register Address Symbol Page Register Address Timer Y, Z mode register TYZMR 80/88 0080 A-D register 00C0 Prescaler Y PREY 00C1 0081 Timer Y secondary TYSC 00C2 0082 00C3 Timer Y primary TYPR 0083 00C4 82/90 Timer Y, Z waveform output control register 0084...

  • Page 11: Chapter 1. Overview

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 1. Overview 1. Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency.

  • Page 12: Performance Outline

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 1. Overview 1.2 Performance Outline Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance Number of basic instructions 89 instructions Shortest instruction execution time 50 ns (f(X ) = 20 MH...

  • Page 13: Block Diagram

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 1. Overview 1.3 Block Diagram Figure 1.1 shows this MCU block diagram. I/O port Port P4 P o r t P 3 Port P0 Port P1 Peripheral functions T i m e r...

  • Page 14: Product Information

    2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. R8C/11 group R8C/Tiny series Memory type: F: Flash memory version Renesas MCU Renesas semiconductors Figure 1.2 Type No., Memory Size, and Package Rev.0.91 2003 Sep 08 page 4 of 184...

  • Page 15: Pin Assignments

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 1. Overview 1.5 Pin Assignments Figure 1.3 shows the pin configuration (top view). PIN CONFIGURATION (top view) 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 /INT / A N /CMP0...

  • Page 16: Pin Description

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 1. Overview 1.6 Pin Description Table 1.3 shows the pin description Table 1.3 Pin description Signal name Pin name I/O type Function Power supply Vcc, Input Apply 2.7 V to 5.5 V to the Vcc pin.

  • Page 17: Chapter 2. Central Processing Unit (Cpu)

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank.

  • Page 18: Address Registers (A0 And A1)

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 2. Central Processing Unit (CPU) 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing.

  • Page 19: Chapter 3. Memory

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 3. Memory 3. Memory Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 00000 to FFFFF The internal ROM is allocated in a lower address direction beginning with address 0FFFF .

  • Page 20: Chapter 4. Special Function Registers (Sfr)

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 4. Special Function Register (SFR) 4. Special Function Register (SFR) Register Symbol After reset A d d r e s s 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 3...
  • Page 21 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 4. Special Function Register (SFR) Address Register Symbol After reset 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C Key input interrupt control register KUPIC XXXXX000 004D...
  • Page 22 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 4. Special Function Register (SFR) Register Symbol After reset Address Timer Y, Z mode register TYZMR 0080 Prescaler Y PREY 0081 Timer Y secondary TYSC 0082 Timer Y primary...
  • Page 23 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 4. Special Function Register (SFR) Register Address Symbol After reset 00C0 A-D register 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE...

  • Page 24: Chapter 5. Reset

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.1 Hardware Reset 5. Reset There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset. 5.1 Hardware Reset There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset.
  • Page 25 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.1 Hardware Reset 0000 Data register(R0) 0000 Data register(R1) 0000 Data register(R2) 0000 Data register(R3) 0000 Address register(A0) 0000 Address register(A1) 0000 Frame base register(FB) 00000 Interrupt table register(INTB) Content of addresses 0FFFE...
  • Page 26 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.1 Hardware Reset 2.7V R E S E T R E S E T Equal to or less than 0.2V M o r e t h a n t d ( P - R ) + 5 0 0 µ s a r e n e e d e d .

  • Page 27: Hardware Reset

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.1 Hardware Reset 5.1.2 Hardware Reset 2 The microcomputer is reset when the voltage at the V input pin drops below Vdet if all of the following conditions hold true.

  • Page 28: Power-On Reset Function

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.1 Hardware Reset 5.1.3 Power-on Reset Function The power-on reset is the function which can reset the microcomputer without the external reset ____________ circuit. The RESET pin should be connected to the V pin via about 5 kΩ...

  • Page 29: Software Reset

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.2 Software Reset, 5.3 Watchdog Timer Reset 5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized.

  • Page 30: Voltage Detection Circuit

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit 5.4 Voltage Detection Circuit The voltage detection circuit has a circuit to monitor the input voltage at the V pin with Vdet. Besides the program, the hardware reset 2 and voltage detection interrupt can be used to check the input voltage at the V pin.
  • Page 31 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit V o l t a g e d e t e c t i o n r e g i s t e r 1 Symbol Address After reset...
  • Page 32 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit Voltage detection interrupt register S y m b o l A d d r e s s A f t e r r e s e t D 4 I N T 0 0 1 F R e s e t i n p u t : 0 0...
  • Page 33 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit 5.0 V 5.0 V x 32 Sampling time fRING (3 to 4 clock) Internal reset signal (D46 bit=1) VC13 bit Set to“1”...
  • Page 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit 5.0V Internal reset signal(D46 bit = 1) VC13 bit Set to "1" by program (voltage detection circuit enabled) VC27 bit CM 10 bit Interrupt acknowledged Voltage detection...

  • Page 35: Voltage Detection Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit 5.4.1 Voltage Detection Interrupt Figure 5.13 shows the block diagram of voltage detection interrupt generation circuit. Refer to 5.4.2, "Exiting Stop Mode on a Voltage Detection Circuit" for Getting out of stop mode due to the voltage detection interrupt.
  • Page 36 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit Voltage detection interrupt generation circuit Voltage detection circuit DF1 to DF0 D42 bit is set to “0”(not detected) by writing a “0” in a program. VC27 When VC27 bit is set to “0”...

  • Page 37: Get Out Of Stop Mode Due To The Voltage Detection Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 5.4 Voltage Detection Circuit 5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt A voltage detection interrupt is generated when the input voltage at the V pin rises to Vdet or more or drops below Vdet if all of the following conditions hold true in stop mode.

  • Page 38: Chapter 6. Clock Generating Circuit

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6. Clock Generating Circuit 6. Clock Generation Circuit The clock generation circuit contains two oscillator circuits as follows: • Main clock oscillation circuit • Ring oscillator (oscillation stop detect function) Table 6.1 lists the clock generation circuit specifications.
  • Page 39 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6. Clock Generating Circuit RING-fast Ring High-speed HR00 oscillator ring oscillator clock HR01=1 RING HR01=0 RING128 1/128 Low-speed CM14 ring oscillator fRING-S  1SIO Voltage detection circuit...
  • Page 40 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6. Clock Generating Circuit System clock control register 0 Symbol Address After reset 0006 Bit symbol Bit name Function Must set to “0” Reserved bit (b1-b0) WAIT peripheral function 0 : Do not stop peripheral function clock in wait mode...
  • Page 41 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6. Clock Generating Circuit Oscillation stop detection register Symbol Address After reset 000C Bit symbol Bit name Function b1 b0 Oscillation stop OCD0 0 0: The function is disabled detection enable bit 0 1: Avoid this setting 1 0: Avoid this setting...
  • Page 42 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6. Clock Generating Circuit High-speed ring control register 0 Symbol Address After reset 0008 Bit symbol Function name High-speed ring enable bit 0: High-speed ring oscillator off HR00 1: High-speed ring oscillator on 0: Low-speed ring oscillator selected...

  • Page 43: Main Clock

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.1 Main Clock The following describes the clocks generated by the clock generation circuit. 6.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.

  • Page 44: Ring Oscillator Clock

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.2 Ring Oscillator Clock 6.2 Ring Oscillator Clock This clock is supplied by a ring oscillator. There are two kinds of ring oscillator: high-speed ring oscil- lator and low-speed ring oscillator.

  • Page 45: Cpu Clock And Peripheral Function Clock

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.3 CPU Clock and Peripheral Function Clock 6.3 CPU Clock and Peripheral Function Clock There are two type clocks: CPU clock to operate the CPU and peripheral function clock to operate the peripheral functions.

  • Page 46: Power Control

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.4 Power Control 6.4 Power Control There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred to as normal operation mode here. 6.4.1 Normal Operation Mode Normal operation mode is further classified into three modes.
  • Page 47 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.4 Power Control Table 6.2 Setting Clock Related Bit and Modes OCD register CM1 register CM0 register Modes OCD2 CM17, CM16 CM06 CM05 High-speed mode Medium- divided by 2 speed...

  • Page 48: Wait Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.4 Power Control 6.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because both are operated by the CPU clock.

  • Page 49: Stop Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.4 Power Control 6.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
  • Page 50 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.4 Power Control Figure 6.6 shows the state transition from normal operation mode to stop mode and wait mode. Figure 6.7 shows the state transition in normal operation mode. Reset CPU operation stopped WAIT...
  • Page 51 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.4 Power Control Ring oscillator mode (main clock is oscillating, ring oscillator is oscillating) Normal operation mode (Main clock is oscillating, ring oscillator is oscillating) 8-division mode Medium-speed mode (divided-by-8 mode)

  • Page 52: Oscillation Stop Detection Function

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.5 Oscillation Stop Detection Function 6.5 Oscillation Stop Detection Function The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD register.
  • Page 53 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 6.5 Oscillation Stop Detection Function Table 6.5 Determination of Interrupt Source (Oscillation Stop Detection or Watchdog Timer Interrupt) Generated Interrupt Source Bit showing interrupt source Oscillation stop detection (a) The OCD3 bit in the OCD register = 1 ( (a) or (b) )

  • Page 54: Chapter 7. Protection

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 7. Protection 7. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected by the PRCR register.

  • Page 55: Chapter 8. Processor Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 8. Processor Mode 8. Processor Mode 8.1 Types of Processor Mode The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure 8.1 shows the PM0 and PM1 register.

  • Page 56: Chapter 9. Bus Control

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 9. Bus 9. Bus During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for access space. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16 bits) units, these spaces are accessed twice in 8-bit units.

  • Page 57: Chapter 10. Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview 10. Interrupt 10.1 Interrupt Overview 10.1.1 Type of Interrupts Figure 10.1 shows types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (Non-maskable interrupt)

  • Page 58: Software Interrupts

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview 10.1.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non- maskable interrupts. • Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction.

  • Page 59: Hardware Interrupts

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview 10.1.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function inter- rupts. (1) Special Interrupts Special interrupts are non-maskable interrupts.

  • Page 60: Interrupts And Interrupt Vector

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview 10.1.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respec- tive interrupt vectors.
  • Page 61 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview • Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table. Table 10.2 Interrupt and Vector Tables in Relocatable Vector Tables Software interrupt Vector address...

  • Page 62: Interrupt Control

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview 10.1.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/ disable the maskable interrupts.

  • Page 63: Interrupt Control Register

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview Interrupt control register Symbol Address After reset KUPIC 004D XXXXX000 ADIC 004E XXXXX000 CMP2IC 0050 XXXXX000 S0TIC, S1TIC 0051 , 0053 XXXXX000 S0RIC, S1RIC 0052...
  • Page 64 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview • I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt.
  • Page 65 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview • Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
  • Page 66 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview • Interrupt Response Time Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the inter- rupt routine is executed.
  • Page 67 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview • Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first.
  • Page 68 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview • Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
  • Page 69 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.1 Interrupt Overview • Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested.

  • Page 70: Int Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. ______ R8C/11 Group 10.2 INT Interrupt ______ 10.2 INT Interrupt ________ 10.2.1 INT0 Interrupt _______ INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN register must be set to “1”...

  • Page 71: Int0 Input Filter

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. ______ R8C/11 Group 10.2 INT Interrupt _______ 10.2.2 INT0 Input Filter _______ The INT0 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the INT0F1 to INT0F0 bits in the INT0F register.

  • Page 72: Int1 Interrupt And Int2 Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. ______ R8C/11 Group 10.2 INT Interrupt ______ ______ 10.2.3 INT1 Interrupt and INT2 Interrupt ______ ______ INT1 interrupts are triggered by INT1 inputs. The edge polarity is selected with the R0EDG bit in the ______ ______ TXMR register.

  • Page 73: Int3 Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. ______ R8C/11 Group 10.2 INT Interrupt ______ 10.2.4 INT3 Interrupt _____ ______ INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to “0” ______ _______ (INT3).
  • Page 74 Under development Preliminary specification Specifications in this manual are tentative and subject to change. ______ R8C/11 Group 10.2 INT Interrupt Timer C control register 0 Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TCC0 009A Bit symbol Function Bit name 0 : Count stop...

  • Page 75: Key Input Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.3 Key Input Interrupt 10.3 Key Input Interrupt _____ _____ A key input interrupt is generated on an input edge of any of the K1 to K1 pins.

  • Page 76: Address Match Interrupt

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.4 Address Match Interrupt 10.4 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt.
  • Page 77 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 10.4 Address Match Interrupt Address match interrupt enable register Symbol Address After reset AIER 0009 XXXXXX00 Bit symbol Bit name Function Address match interrupt 0 0 : Interrupt disabled AIER0 enable bit...

  • Page 78: Chapter 11. Watchdog Timer

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 11. Watchdog Timer 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve reliability of a system.
  • Page 79 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 11. Watchdog Timer Watchdog timer control register Symbol Address After reset 000F 000XXXXX Bit symbol Bit name Function High-order bit of watchdog timer (b4-b0) Reserved bit Must set to “0”...

  • Page 80: Chapter 12. Timers

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12. Timers 12. Timers The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has input capture and output compare.

  • Page 81: Timer X

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) 12.1 Timer X The Timer X is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer X. Figures 12.2 and 12.3 show the Timer X-related registers.
  • Page 82 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) Prescaler X Register Symbol Address After reset PREX 008C Mode Function Setting range Internal count source is counted Timer mode to FF Internal count source is counted Pulse output mode...

  • Page 83: Timer Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) 12.1.1 Timer Mode In this mode, the timer counts an internally generated count source (See “Table 12.2 Timer Mode Specifications”). Figure 12.4 shows the TXMR register in timer mode. Table 12.2 Timer Mode Specifications Item Specification...

  • Page 84: Pulse Output Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) 12.1.2 Pulse Output Mode In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode Specifications”).

  • Page 85: Event Counter Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) 12.1.3 Event Counter Mode In this mode, the timer counts an external signal fed to INT1/CNTR pin (See “Table 12.4 Event Counter Mode Specifications”).

  • Page 86: Pulse Width Measurement Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) 12.1.4 Pulse Width Measurement Mode In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See “Table 12.5 Pulse Width Measurement Mode Specifications”).
  • Page 87 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) n = high-level: the contents of TX register, low-level: the contents of PREX register FFFF Count start Underflow Count stop Count stop Count restart 0000...

  • Page 88: Pulse Period Measurement Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) 12.1.5 Pulse Period Measurement Mode In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See “Table 12.6 Pulse Period Measurement Mode Specifications”).
  • Page 89 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.1 Timer (Timer X) Underflow signal of prescaler X Set to "1" by program “1” TXS bit in TXMR register “0” Starts counting CNTR0 pin “1”...

  • Page 90: Timer Y

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) 12.2 Timer Y Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer Y Secondary.
  • Page 91 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) Prescaler Y register Symbol Address After reset PREY 0081 Mode Function Setting range Internal count source or CNTR1 Timer mode to FF input is counted Programmable...
  • Page 92 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) Timer Y, Z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset 0084 Bit symbol Bit name Function...

  • Page 93: Timer Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) 12.2.1 Timer Mode In this mode, the timer counts an internally generated count source (see “Table 12.7 Timer Mode Specifications”). An external signal input to the CNTR1 pin can be counted. The TYSC register is unused in timer mode.
  • Page 94 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) Timer Y, Z mode register Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TYZMR 0080 Bit symbol Function Bit name Timer Y operation...

  • Page 95: Programmable Waveform Generation Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) 12.2.2 Programmable Waveform Generation Mode In this mode, an signal output from the TY pin is inverted each time the counter underflows, while the values in the TYPR register and TYSC register are counted alternately (see “Table 12.8 Program- mable Waveform Generation Mode Specifications”).
  • Page 96 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) Timer Y, Z mode register Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TYZMR 0080 Bit symbol Function Bit name Timer Y operation...
  • Page 97 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.2 Timer (Timer Y) Set to "1" by program "1" TYS bit in TYZMR register "0" Count starts Count source Prescaler Y underflow signal Timer Y Timer Y secondary...

  • Page 98: Timer Z

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) 12.3 Timer Z Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer Z Secondary.
  • Page 99 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Prescaler Z register Symbol Address After reset PREZ 0085 Mode Function Setting range Timer mode Internal count source or Timer Y to FF underflow is counted Programmable...
  • Page 100 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Timer Y, Z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset 0084 Bit symbol Bit name Function...

  • Page 101: 1Timer Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) 12.3.1 Timer Mode In this mode, the timer counts an internally generated count source or Timer Y underflow (see “Table 12.9 Timer Mode Specifications”).
  • Page 102 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Timer Y, Z mode register Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TYZMR 0080 Bit symbol Function Bit name TYMOD0...

  • Page 103: Programmable Waveform Generation Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) 12.3.2 Programmable Waveform Generation Mode In this mode, an signal output from the TZ pin is inverted each time the counter underflows, while the values in the TZPR register and TZSC register are counted alternately (see “Table 12.10 Pro- grammable Waveform Generation Mode Specifications”).
  • Page 104 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Timer Y, Z mode register Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TYZMR 0080 Bit symbol Function Bit name TYMOD0...

  • Page 105: Programmable One-Shot Generation Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) 12.3.3 Programmable One-shot Generation Mode In this mode, upon program command or external trigger input (input to the INT0 pin), the microcom- puter outputs the one-shot pulse from the TZ pin (see “Table 12.11 Programmable One-shot Generation Mode Specifications”).
  • Page 106 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Timer Y, Z mode register Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TYZMR 0080 Bit symbol Bit name Function TYMOD0...
  • Page 107 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Set to "1" by program "1" TZS bit in TYZMR register "0" Set to "0" when Set to "1" by INT0 pin Set to "1"...

  • Page 108: Programmable Wait One-Shot Generation Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) 12.3.4 Programmable Wait One-shot Generation Mode In this mode, upon program or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZ pin after waiting for a given length of time (see “Table 12.12 Programmable Wait One-shot Generation Mode Specifications”).
  • Page 109 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Timer Y, Z mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset TYZMR 0080 Bit symbol Function Bit name TYMOD0...
  • Page 110 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.3 Timer (Timer Z) Set to "1" by program "1" TZS bit TYZMR Set to "0" when register counting completed "0" Set to "1" by program, or set to "1" by INT0 pin input trigger "1"...

  • Page 111: Timer C

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) 12.4 Timer C Timer C is a 16-bit timer. Figure 12.28 shows a block diagram of Timer C. Figure 12.29 shows a block diagram of PWM waveform generation unit.
  • Page 112 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) T C C 1 4 T C C 1 5 C o m p a r e 0 i n t e r r u p t s i g n a l C o m p a r e 1 i n t e r r u p t s i g n a l T C C 1 6 T C C 1 7...
  • Page 113 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) Timer C register (b15) (b8) Symbol Address After reset 0091 -0090 0000 Function Internal count source is counted "000 can be read out by reading when TCC00 bit = 0 (stops counting) 16 "...
  • Page 114 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) Timer C control register 1 Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TCC1 009B Bit symbol Function Bit name b1 b0...

  • Page 115: Input Capture Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) 12.4.1 Input Capture Mode This mode uses an edge input to TC pin or the f clock as trigger to latch the timer value and RING128 generates an interrupt request.
  • Page 116 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) Overflow FFFF Count start Measurement value 2 Measure- ment Measurement value 1 value 3 0000 Time Set to "0" by Set to "1"...

  • Page 117: Output Compare Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) 12.4.2 Output Compare Mode In this mode, an interrupt request is generated when the value of TC register matches the value of TM0 or TM1 register.
  • Page 118 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 12.4 Timer (Timer C) Match Set value in TM1 register Count start Match Match Set value in TM0 register 0000 Time Set to “1” by program “1”...

  • Page 119: Chapter 13. Serial I/O

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13. Serial I/O 13. Serial I/O 13. Serial I/O Serial I/O is configured with two channels: UART0 to UART1. UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
  • Page 120 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13. Serial I/O Clock synchronous type Clock PRYE=0 UART (7 bits) synchronous UARTi receive register UART (7 bits) UART (8 bits) type disabled RxDi UART UART (9 bits) enabled...
  • Page 121 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13. Serial I/O 1, 2 UARTi transmit buffer register (i=0, 1) Symbol Address After reset (b15) (b8) U0TB 00A3 -00A2 Indeterminate U1TB 00AB -00AA Indeterminate Function Transmit data...
  • Page 122 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13. Serial I/O UARTi transmit/receive mode register (i=0, 1) Symbol Address After reset U0MR 00A0 U1MR 00A8 Function Bit name symbol SMD0 b2 b1 b0 Serial I/O mode 0 0 0 : Serial I/O disabled select bit...
  • Page 123 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13. Serial I/O UARTi transmit/receive control register 1 (i=0, 1) Symbol Address After reset U0C1 00A5 U1C1 00AD Function symbol name Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled Transmit buffer...

  • Page 124: Clock Synchronous Serial I/O Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode 13.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. This mode can be selected with UART0.
  • Page 125 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function U0TB 0 to 7 Set transmission data U0RB...
  • Page 126 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode • Example of transmit timing (when internal clock is selected) Transfer clock “1” U0C1 register TE bit Write data to U0TB register “0”...

  • Page 127: Polarity Select Function

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode 13.1.1 Polarity Select Function Figure 13.7 shows the polarity of the transfer clock. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity.

  • Page 128: Continuous Receive Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode 13.1.3 Continuous Receive Mode The unit is configured to continuous receive mode by setting the U0RRM bit in the UCON register to “1”...

  • Page 129: Clock Asynchronous Serial I/O (Uart) Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode 13.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format.
  • Page 130 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Table 13.5 Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data UiRB 0 to 8...
  • Page 131 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock UiC1 register “1”...

  • Page 132: Txd10/Rxd1 Select Function (Uart1)

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source “1”...

  • Page 133: Chapter 14. A-D Converter

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. A-D Converter 14. A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. The analog inputs share the pins with P0 to P0 and P1 to P1...
  • Page 134 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. A-D Converter CKS1=1 φ CKS0=1 A-D conversion rate CKS1=0 CKS0=0 selection VCUT=0 VCUT=1 Resistor ladder Successive conversion register ADCON0 AD register Decoder Data bus Comparator CH2,CH1,CH0=000 CH2,CH1,CH0=001...
  • Page 135 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. A-D Converter A-D control register 0 Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 ADCON0 00D6 00000XXX Bit symbol Bit name Function Analog input pin select bit...
  • Page 136 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. A-D Converter A-D control register 2 Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 ADCON2 00D4 0 0 0 Bit symbol Bit name Function...

  • Page 137: One-Shot Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. One-shot mode 14.1 One-shot Mode In one-shot mode, the input voltage on one selected pin is A-D converted once. Table 14.2 lists the specifications of one-shot mode.
  • Page 138 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. One-shot mode Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 ADCON0 00D6 00000XXX Bit symbol Bit name Function See Note 4 Analog input pin select bit 0 : One-shot mode A-D operation mode...

  • Page 139: Repeat Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. Repeat mode 14.2 Repeat Mode In repeat mode, the input on one selected pin is A-D converted repeatedly. Table 14.3 lists the speci- fications of repeat mode.
  • Page 140 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. Repeat mode A-D control register 0 Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 ADCON0 00D6 00000XXX Bit symbol Bit name Function Analog input pin select bit...

  • Page 141: Sample And Hold

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 14. Sample and Hold mode 14.3 Sample and Hold If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin is increased to 28 cycles for 8-bit resolution or 33 cycles for 10-bit resolution.

  • Page 142: Chapter 15. Programmable I/O Ports

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports 15. Programmable I/O Ports 15. 1 Description The programmable input/output ports (hereafter referred to as “I/O ports”) consist of 22 lines P0, P1, P3 to P3 , P3 , and P4...
  • Page 143 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports Pull-up selection Direction regiister "1" Output Port latch Data bus Analog input Pull-up selection to P0 Direction register Port latch Data bus Analog input Pull-up selection...
  • Page 144 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports Pull-up selection Direction register Data bus Port latch Select drive capacity Input to respective peripheral functions Analog input Pull-up selection Direction...
  • Page 145 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports Pull-up selection Direction register "1" Output Port latch Data bus Select drive capactiy Input to respective peripheral functions , P3 Puu-up selection Direction register...
  • Page 146 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports Pull-up selection Direction register Port latch Data bus Digital Input to respective peripheral functions Filter Pull-up selection Direction register "1"...
  • Page 147 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports Data bus Clocked inverter (Note 2) Data bus Notes: 1. When CM05=1, CM10=1, or CM13=0, the clocked inverter is cutoff. 2.
  • Page 148 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports 1, 2, 3 Port Pi direction register (i=0, 1, 3, 4) Symbol Address After reset 00E2 00E3 00E7 00EA...
  • Page 149 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports Pull-up control register 0 Symbol Address After reset PUR0 00FC 00XX0000 Bit symbol Bit name Function PU00 to P0 pull-up 0 : Not pulled high PU01 to P0...

  • Page 150: Unassigned Pin Handling

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports 15.2 Unassigned Pin Handling Table 15.1 lists the handling of unassigned pins. Table 15.1 Unassigned Pin Handling Pin name Connection After setting for input mode, connect every pin to V...

  • Page 151: Chapter 16. Electrical Characteristics

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 16. Electrical Characteristics 16. Electrical Characteristics Table 16.1 Absolute Maximum Ratings Symbol Parameter Condition Rated value Unit Supply voltage -0.3 to 6.5 -0.3 to 6.5 Analog supply voltage Input voltage -0.3 to V...
  • Page 152 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 16. Electrical Characteristics Table 16.3 A-D Conversion Characteristics Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. Resolution – Absolute 10 bit mode f(XIN)=øAD=10 MHz, Vref=Vcc=5.0V ±3 –...
  • Page 153 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 16. Electrical Characteristics Table 16.6 Power-on Reset Circuit Electrical Characteristics Standard Symbol Measuring condition Parameter Unit Min. Typ. Max. Power-on reset start time Vcc<0.5V Power-on reset cancel operation start voltage Hardware reset cancel operation start voltage...
  • Page 154 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 16. Electrical Characteristics Table 16.9 Electrical Characteristics (1) [Vcc=5V] Standard Measuring condition Parameter Symbol Unit Min. Typ. Max. "H" output voltage Except XOUT 200µA 1 mA Drive ability HIGH 500µA...
  • Page 155 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 16. Electrical Characteristics Table 16.10 Electrical Characteristics (2) [Vcc=5V] Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. =20 MHz (square wave) High-speed High-speed ring oscillator off mode Low-speed ring oscillator on=100 kHz No division...
  • Page 156 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 16. Electrical Characteristics Table 16.11 Electrical Characteristics (3) [Vcc=3V] Standard Measuring condition Parameter Symbol Unit Min. Typ. Max. "H" output voltage Except XOUT Drive ability HIGH 0.1 mA Drive ability LOW 50 µA...
  • Page 157 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 16. Electrical Characteristics Table 16.12 Electrical Characteristics (4) [Vcc=3V] Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. =20 MHz (square wave) High-speed High-speed ring oscillator off mode Low-speed ring oscillator on=100 kHz No division...

  • Page 158: Chapter 17. Flash Memory Version

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17. Flash Memory Version 17. Flash Memory Version 17.1 Overview The flash memory version has two modes—CPU rewrite and standard serial input/output—in which its flash memory can be operated on.

  • Page 159: Memory Map

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17. Memory Map 17.2 Memory Map The ROM in the flash memory version is separated between a user ROM area and a boot ROM area (reserved area).

  • Page 160: Functions To Prevent Flash Memory From Rewriting

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.3 Functions To Prevent Flash Memory from Rewriting 17.3 Functions To Prevent Flash Memory from Rewriting 17.3 Functions To Prevent Flash Memory from Rewriting To prevent the flash memory from being read or rewritten easily, standard serial input/output mode has an ID code check function.

  • Page 161: Cpu Rewrite Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode 17.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.

  • Page 162: Ew0 Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode 17.4 CPU Rewrite Mode 17.4.1 EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled), ready to accept commands.
  • Page 163 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode Figure 17.3 shows the FMR0 and FMR1 registers. Figure 17.4 shows the FMR4 register. • FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” during programming, eras- ing, or erase-suspend mode;...
  • Page 164 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset FMR0 01B7 XX000001 Bit name Function Bit symbol...
  • Page 165 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode Flash memory control register 1 Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 FMR1 01B5 0100XX0X Bit name Function Bit symbol...
  • Page 166 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode Figures 17.5 and 17.6 show the setting and resetting of EW0 mode and EW1 mode, respectively. EW0 mode operation procedure Rewrite control program Set the FMR01 bit by writing “0”...
  • Page 167 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode Ring oscillator mode ( main clock stop) program Transfer a ring oscillator mode (main clock stop) Set the FMR01 bit by writing “0” and then “1” program to any area other the flash memory (CPU rewrite mode enabled) Set FMSTP bit to “1”...

  • Page 168: Software Commands

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode 17.4.3 Software Commands Software commands are described below. The command code and data must be read and written in 8-bit units. Table 17.4 Software Commands First bus cycle Second bus cycle...
  • Page 169 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode • Program Command This command writes data to the flash memory in one byte units. Write ‘40 ’ in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start.
  • Page 170 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode • Block Erase Write ‘20 ’ in the first bus cycle and write ‘D0 ’ to the uppermost address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start.
  • Page 171 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode <EW0 Mode> Start Interrupt FMR40=1 FMR40=1 Write the command code ‘20 ’ FMR46=1? Write ‘D0 ’ to the uppermost block address Access to flash memory FMR00=1? FMR41=0...

  • Page 172: Status Register

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode 17.4.4 Status Register The status register indicates the operating status of the flash memory and whether an erase or pro- gramming operation terminated normally or in error.

  • Page 173: Full Status Check

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode 17.4.5 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur- rence of each specific error.
  • Page 174 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.4 CPU Rewrite Mode Full status check FMR06 =1 (1) Execute the Clear Status Register command to set Command these status flags to “0”. FMR07=1? sequence error (2) Re-execute the command after checking that it is...

  • Page 175: Standard Serial I/O Mode

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.5 Standard Serial I/O Mode 17.5 Standard Serial I/O Mode In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer suitable for this microcomputer.
  • Page 176 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.5 Standard Serial I/O Mode Table 17.7 Pin Functions (Flash Memory Standard Serial I/O Mode) Name Description Apply the voltage guaranteed for Program and Erase to Vcc pin and Power input 0V to Vss pin.
  • Page 177 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.5 Standard Serial I/O Mode 24 23 22 21 20 19 18 17 MODE R8C/11 1 2 3 4 5 6 7 8 Connect oscillator circuit Mode Setting...
  • Page 178 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 17.5 Standard Serial I/O Mode • Example of Circuit Application in the Standard Serial I/O Mode Figures 17.13 and 17.14 show examples of circuit application in standard serial I/O mode 1 and mode 2, respectively.

  • Page 179: Chapter 18. On-Chip Debugger

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 18. On-chip Debugger 18. On-chip debugger The microcomputer has functions to execute the on-chip debugger. Refer to "Appendix 2 Connecting examples for serial writer and on-chip debugging emulator". Refer to the respective on-chip debugger manual for the details of the on-chip debugger.

  • Page 180: Chapter 19. Usage Notes

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes 19. Usage Notes 19.1 Stop Mode and Wait Mode When entering stop mode or wait mode, an instruction queue pre-reads 4 bytes from the WAIT instruction or an instruction that sets the CM10 bit in the CM1 register to “1”...
  • Page 181 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes Interrupt factor change 1, 2 Interrupt disabled Change interrupt source (including mode change of peripheral functions) Set IR bit to “0” (interrupt not requested) using MOV instruction 1, 2 Enable interrupt...

  • Page 182: Changing Interrupt Control Register

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes 19.2.6 Changing Interrupt Control Register (1) Each interrupt control register can only be modified while no interrupt requests corresponding to that register are generated. If interrupt requests managed by any interrupt control register are likely to occur, disable the interrupts before changing the interrupt control register.

  • Page 183: Timers

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes 19.3 Timers 19.3.1 Timers X, Y and Z (1) Timers X, Y and Z stop counting after reset. Therefore, a value must be set to these timers and prescalers before starting counting.

  • Page 184: Serial I/O

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes 19.4 Serial I/O (1) When reading data from the UiRB (i=0,1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode.

  • Page 185: A-D Converter

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes 19.5 A-D Converter (1) When writing to each bit but except bit 6 in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register, A/D conversion must be stopped (before a trigger occurs).

  • Page 186: Flash Memory Version

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes 19.6 Flash Memory Version 19.6.1 CPU Rewrite Mode (1) Operation Speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 5 MHz or less for CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register.
  • Page 187 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes (7) Stop Mode When shifting to stop mode, the following settings are required: • Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the CM10 bit to “1”...

  • Page 188: Noise

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 19. Usage Notes 19.7 Noise (1) Bypass Capacitor between V and V Pins Insert a bypass capacitor (at least 0.1 µF) between V and V pins as the countermea- sures against noise and latch-up.

  • Page 189: Chapter 20. Usage Notes For On-Chip Debugger

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group 20. Usage Notes for On-chip Debugger 20. Usage notes for on-chip debugger When using the on-chip debugger to develop the R8C/11 group program and debug, pay the following attention.

  • Page 190: Appendix 1 Package Dimensions

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions 32P6U-A Plastic 32pin 7 7mm body LQFP EIAJ Package Code JEDEC Code Weight(g) Lead Material – Cu Alloy LQFP32-P-0707-0.80 Recommended Mount Pad...

  • Page 191: Appendix 2 Connecting Examples For Serial Writer And On-Chip Debugging Emulator

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator R8C/11 Group Appendix 2. Connecting examples for serial writer and on-chip debugging emulator Appendix figure 2.1 shows connecting examples with USB Flash Writer and appendix figure 2.2 shows connecting examples with M16C Flash Starter.
  • Page 192 Under development Preliminary specification Specifications in this manual are tentative and subject to change. Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator R8C/11 Group Appendix figure 2.3 shows connecting examples with emulator E7. 24 23 22 21 20 19 18 17 MODE R8C/11 1 2 3 4 5 6 7 8...

  • Page 193: Register Index

    Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group Register Index Register Index AD 122 P0 133 ADCON0 121, 124, 126 P1 133 ADCON1 121, 124, 126 P3 133 ADCON2 122 P4 133 ADIC 49 PD0 133 AIER 63...
  • Page 194 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/11 Group Register Index TYIC 49 TYPR 77 TYSC 77 TYZMR 58, 76, 80, 82, 84, 88, 90, 92, 95 TYZOC 77, 85 TZIC 49 TZPR 85 TZSC 85 U0BRG 107 U0C0 108...
  • Page 195 R8C/11 Group Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 0.91 – First edition issued Sep 08, 2003...
  • Page 196 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL R8C/11 Group Publication Data : Rev.0.91 Sep 08, 2003 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
  • Page 197 R8C/11 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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