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M16C/5L Group, M16C/56 Group
13.4.2
Count Source Protection Mode Disabled
The CPU clock is used as the watchdog timer count source when the count source protection mode is
disabled.
Table 13.3 lists the specifications of watchdog timer when the count source protection mode is disabled.
Table 13.3
Watchdog Timer Specifications (When Count Source Protection Mode is Disabled)
Item
Count source
Count operation
Watchdog timer
cycle
Watchdog timer
counter refresh
timing
Count start
conditions
Count stop
conditions
Operations when the
watchdog timer
underflows
Note:
1.
Writing 00h and then FFh to the WDTR register refreshes the watchdog timer counter, but not the
prescaler. Therefore, marginal differences in the watchdog timer cycle can be expected. The
prescaler is initialized by a reset.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
CPU clock
Decrements
When the CM07 bit in the CM0 register is 0 (main clock, PLL clock, 40 MHz on-chip
oscillator clock, 125 kHz on-chip oscillator clock):
Prescaler divider factor (n) watchdog timer count value (32768)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -
n = 16 or 128, selected by the WDC7 bit in the WDC register
Example: When CPU clock frequency is 16 MHz and the prescaler divider factor is
16, the watchdog timer cycle is approximately 32.8 ms.
When the CM07 bit is 1 (sub clock):
Prescaler divider factor (2) watchdog timer count value (32768)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -
•
Resets (refer to 6. "Resets" for details)
•
Write 00h, and then FFh to the WDTR register.
•
Watchdog timer underflow
Set the WDTON bit in the OFS1 address to select the watchdog timer state after
reset.
•
When the WDTON bit is 1 (watchdog timer is in a stop state after reset):
The watchdog timer and prescaler stop after reset and the watchdog timer starts
counting by writing to the WDTS register.
•
When the WDTON bit is 0 (watchdog timer starts automatically after reset):
The watchdog timer and prescaler start counting automatically after reset.
•
Wait mode
•
Stop mode
•
While executing software commands in EW1 mode, except when executing the
suspend function.
The count resumes from the value held after exiting the modes above.
•
When the PM12 bit in the PM1 register is 0, a watchdog timer interrupt is
generated.
•
When the PM12 bit in the PM1 register is 1, the watchdog timer is reset. (refer to
6.4.7 "Watchdog Timer Reset" for details)
Specification
×
CPU clock
(1)
×
CPU clock
13. Watchdog Timer
(1)
Page 208 of 803
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