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M16C/5L Group, M16C/56 Group
7.4
Operations
7.4.1
Digital Filter
A digital filter can be used to monitor VCC input voltage. For voltage detector 2, the digital filter is
enabled when the VW2C1 bit in the VW2C register is set to 0 (digital filter enabled).
fOCO-S divided by 1, 2, 4, or 8 is selected as a sampling clock. When using the digital filter, set the
CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on).
The VCC input level is sampled by the digital filter for every sampling clock. When the same sampled
level is detected three times in a row, at the third sampling timing, the internal reset signal goes low or a
voltage monitor 2 interrupt request is generated. Therefore, when the digital filter is used, the time from
when the VCC input voltage level passes Vdet2 until when a reset or an interrupt is generated is up to
three cycles of the sampling clock.
Since fOCO-S stops in stop mode, the digital filter does not function. When using voltage detector 2 to
exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled).
Figure 7.2 shows Digital Filter Operation Example.
VCC
Vdet2
VC13 bit in
the VCR1 register
Sampling timing of
the digital filter
VW2C2 bit in
the VW2C register
Internal signal
(Voltage monitor 2
interrupt request)
The above assumes the following:
•
The VW12E bit in the VWCE register is 1 (voltage detector 2 enabled).
•
The VW2C0 bit in the VW2C register is 1 (voltage monitor 2 interrupt/reset enabled).
•
The VW2C1 bit in the VW2C register is 0 (digital filter enabled).
•
The VW2C6 bit in the VW2C register is 0 (voltage monitor 2 interrupt at Vdet2 passage).
Figure 7.2
Digital Filter Operation Example
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Up to 3 cycles of the sampling clock
Up to 3 cycles of the sampling clock
Set to 0 by a program
7. Voltage Detector
Page 83 of 803
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