Renesas M16C/50 Series User Manual page 98

M16C/5L Group, M16C/56 Group
Table 6.2 Classification of SFRs Which are Reset
SFR
SFR (A) OSDR bit in the RSTFR register
Registers VCR1, VCR2, and VW0C
SFR (B)
Bits VW2C2 and VW2C3 in the VW2C register
SFR (C) VD2LS register
SFR (D) Bits CM20, CM21, and CM27 in the CM2 register
Table 6.3 I/O Pins
Pin
RESET
VCC
XIN
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
I/O
Input Hardware reset input
Power input. The power-on reset, voltage monitor 0 reset, and voltage
Input
monitor 2 reset are generated by monitoring VCC.
Main clock input. The oscillator stop detect reset is generated by
Input
monitoring the main clock.
Register and Bit
Function
6. Resets
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