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M16C/5L Group, M16C/56 Group
18. Timer S
18.1
Introduction
Timer S has an input capture/output compare function (IC/OC). The input capture (IC) is used for time
measurement and the output compare (OC) is used for waveform generation. The IC/OC has one 16-bit
free-running base timer and eight channels for time measurement and waveform generation.
Table 18.1 lists the specifications of the IC/OC.
Table 18.1
IC/OC Specifications
Item
Measurement channels
Trigger input edges
Time
measurement
Digital filter function
(1)
function
Prescaler function
Gate function
Digital debounce filter
Waveform generating
channels
Waveform generation
functions
Waveform
generation
Output level select function
function
when there is a compare-
(1)
match
Selectable port function
Other functions
Bit length
Count sources
Base timer
Count operations
Base timer reset conditions
IC/OC channel interrupts
Interrupts
IC/OC base timer interrupts
j = 0 to 7
Note:
1.
The time measurement function shares pins with the waveform generation function. Either the time
measurement function or waveform generation function is selectable for each channel.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
8 channels (channels 0 to 7)
Selectable from rising edge, falling edge, or both edges of the
INPC1_j pin
8 channels (channels 0 to 7)
2 channels (channels 6 and 7)
2 channels (channels 6 and 7)
1 channel (channel 7)
8 channels (channels 0 to 7)
Single-phase waveform output, inverted waveform output, and
SR waveform output
The output level can be changed from low to high or high to
low.
Waveform output port or programmable I/O port selectable
Selectable initial output level
Invertible output waveform
16 bits
f1TIMS or f2TIMS divided by (n + 1), two-phase pulse input
divided by (n + 1)
n is a G1DV register setting value from 0 to 255.
There is no division when n = 0.
Increment, increment/decrement, two-phase pulse signal
processing
•
Base timer value matches the G1PO0 register value (RST1)
Low is input to external interrupt pin INT1 (RST2)
•
•
Base timer value matches the G1BTRR register value
(RST4)
6 (IC/OC channel 0 interrupt, IC/OC channel 1 interrupt, IC/OC
channel 2 interrupt, IC/OC channel 3 interrupt, IC/OC interrupt
0 (channels 0 to 7), IC/OC interrupt 1 (channels 0 to 7))
1 (The base timer interrupt is generated by base timer
overflow, or by a base timer reset request that occurs when the
G1BTRR register matches the base timer.)
Specification
Page 344 of 803
18. Timer S
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