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M16C/5L Group, M16C/56 Group
16. Timer B
16.1
Introduction
Timer B consists of timers B0 to B2. Each timer operates independently of the others. Table 16.1 lists
Timer B Specifications, Figure 16.1 shows Timer A and B Count Sources, Figure 16.2 shows the Timer B
Configuration, Figure 16.3 shows the Timer B Block Diagram, and Table 16.2 lists the I/O Ports.
Table 16.1
Timer B Specifications
Item
Configuration
16-bit timer × 3
Operating modes
Interrupt source
Overflow/underflow/active edge of measurement pulse × 3
Clock Generator
Main clock
oscillator
or PLL frequency
synthesizer
40 MHz
on-chip
Divider
oscillator
125 kHz
fOCO-S
on-chip
oscillator
fC
Sub clock
oscillator
Set the CPSR bit in the CPSRF
register to 1 (prescaler reset).
Figure 16.1
Timer A and B Count Sources
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
•
Timer mode
The timer counts an internal count source.
•
Event counter mode
The timer counts pulses from an external device, or overflows and underflows of other timers.
•
Pulse period/pulse width measurement modes
The timer measures pulse periods or pulse widths of an external signal.
fOCO-F
CM21
0
FRA01
1
0
1
1/32
Reset
Specification
fOCO-F
f1TIMAB
f2TIMAB
1/2
TCDIV00
1
1/8
f1
0
Timer AB divider
fOCO-S
fC32
CM21
PCLK0
FRA01
TCDIV00 : Bit in the TCKDIVC0 register
fOCO-F
PCLK0
f1TIMAB
1
or
0
f2TIMAB
f8TIMAB
f32TIMAB
1/4
f64TIMAB
1/2
fOCO-S
fC32
: Bit in the CM2 register
: Bit in the PCLKR register
: Bit in the FRA0 register
Page 279 of 803
16. Timer B
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