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11.3.10
Pin Assignment Control Register (PACR) ....................................................................... 159
11.3.11
Port Pi Register (Pi) (i = 0 to 3, 6 to 10) .......................................................................... 160
11.3.12
Port Pi Direction Register (PDi) (i = 0 to 3, 6 to 10) ......................................................... 161
11.4
Peripheral Function I/O............................................................................................................. 162
11.4.1
Peripheral Function I/O and Port Direction Bits ............................................................... 162
11.4.2
Priority Level of Peripheral Function I/O .......................................................................... 162
11.4.3
Digital Debounce Filters .................................................................................................. 163
11.5
Unassigned Pin Handling ......................................................................................................... 165
11.6
Notes on Programmable I/O Ports............................................................................................ 166
11.6.1
Pin Assignment Control ................................................................................................... 166
Influence of SD ................................................................................................................ 166
11.6.2
11.6.3
Input Voltage Threshold ................................................................................................... 166
12. Interrupts .............................................................................................. 167
12.1
Introduction ............................................................................................................................... 167
12.2
Registers................................................................................................................................... 168
12.2.1
Processor Mode Register 2 (PM2) .................................................................................. 170
12.2.2
Interrupt Control Register 1
(BCNIC/TMOSIC, DM0IC to DM3IC, KUPIC,ADIC, S0TIC to S2TIC, S0RIC to S3RIC,
TA0IC to TA4IC, TB0IC to TB2IC, S4TIC/RTCCIC, S4RIC, C0WIC,S3TIC/C0EIC,
RTCTIC C0RIC, C0TIC, C0FRIC, C0FTIC, ICOC0IC, ICOCH0IC, ICOC1IC/IICIC,
ICOCH1IC/SCLDAIC, ICOCH2IC to ICOCH3IC, BTIC) .................................................. 171
12.2.3
Interrupt Control Register 2
(INT3IC, INT5IC, INT4IC, INT0IC to INT2IC) .................................................................. 172
12.2.4
Interrupt Source Select Register 3 (IFSR3A) .................................................................. 173
12.2.5
Interrupt Source Select Register 2 (IFSR2A) .................................................................. 174
12.2.6
Interrupt Source Select Register (IFSR) .......................................................................... 175
12.2.7
Address Match Interrupt Enable Register (AIER) ............................................................ 176
12.2.8
Address Match Interrupt Enable Register 2 (AIER2) ....................................................... 176
12.2.9
Address Match Interrupt Register i (RMADi) (i = 0 to 3) .................................................. 177
12.2.10
NMI Digital Debounce Register (NDDR) ......................................................................... 178
12.2.11
P1_7 Digital Debounce Register (P17DDR) .................................................................... 178
12.3
Types of Interrupts .................................................................................................................... 179
12.4
Software Interrupts ................................................................................................................... 180
12.4.1
Undefined Instruction Interrupt ........................................................................................ 180
12.4.2
Overflow Interrupt ............................................................................................................ 180
12.4.3
BRK Interrupt ................................................................................................................... 180
12.4.4
INT Instruction Interrupt ................................................................................................... 180
12.5
Hardware Interrupts .................................................................................................................. 181
12.5.1
Special Interrupts ............................................................................................................. 181
12.5.2
Peripheral Function Interrupts ......................................................................................... 181
12.6
Interrupts and Interrupt Vectors ................................................................................................ 182
12.6.1
Fixed Vector Tables ......................................................................................................... 182
A- 5
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