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M16C/5L Group, M16C/56 Group
RXDi
switching circuit
Clock source selection
CLK1 to CLK0
00
f1SIO or f2SIO
01
f8SIO
10
f32SIO
CKPOL
CLK
polarity
CLKi
inverting
circuit
CTS / RTS selected
CTSi / RTSi
(1)
CRS
0
n: values set to the U0BRG register
i = 0 to 4
Notes:
1. The CTS/RTS pin is not available for UART4.
2. Special modes are used only for UART2.
Figure 21.1
UARTi Block Diagram
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
OCOSEL0 or OCOSEL1
0
f1
1
fOCO-F
RXD polarity
UART reception
1/16
CKDIR
UiBRG
Internal
register
0
1 / (n + 1)
1/16
1
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CTS / RTS disabled
1
CTS / RTS disabled
0
1
CRD
VSS
PCLK1
f2SIO
0
1/2
1/2
f1SIO
1
1/8
(2)
SMD2 to SMD0
100, 101, 110
Reception
Clock sync type
control
circuit
001, 010
UART transmission
Transmission
100, 101, 110
control circuit
Clock sync type
001, 010
0
1
CKDIR
RTSi
CTSi
PCLK1: Bit in the PCLKR register
SMD2 to SMD0, CKDIR: Bits in the UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register
OCOSEL1, OCOSEL0: Bits in the UCLKSEL00 register
21. Serial Interface UARTi (i = 0 to 4)
f1SIO or f2SIO
f8SIO
1/4
f32SIO
Receive
Transmit/
clock
receive
unit
Transmit
clock
TXDi
TXD
polarity
switching
circuit
Page 432 of 803
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