Renesas M16C/50 Series User Manual page 311

M16C/5L Group, M16C/56 Group
15.4 Interrupts
Refer to individual operation examples for interrupt request generating timing.
Refer to 12.7 "Interrupt Control" for details of interrupt control. Table 15.18 lists Timer A Interrupt Related
Registers.
Table 15.18 Timer A Interrupt Related Registers
Address
0055h Timer A0 Interrupt Control Register
0056h Timer A1 Interrupt Control Register
0057h Timer A2 Interrupt Control Register
0058h Timer A3 Interrupt Control Register
0059h Timer A4 Interrupt Control Register
The IR bit in the TAiIC register may become 1 (interrupt requested) when the TMOD1 bit in the TAiMR
register is changed from 0 to 1 (change from timer mode or event counter mode to one-shot timer mode,
PWM mode, or programmable output mode). Make sure to follow the procedure below when setting the
TMOD1 bit to 1. Refer to 12.13 "Notes on Interrupts" for details.
(1)
Set bits ILVL2 to ILVL0 in the TAiIC register to 000b (interrupt disabled).
(2)
Set the TAiMR register.
(3)
Set the IR bit in the TAiIC register to 0 (interrupt not requested).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Register Symbol Reset Value
TA0IC XXXX X000b
TA1IC XXXX X000b
TA2IC XXXX X000b
TA3IC XXXX X000b
TA4IC XXXX X000b
15. Timer A
Page 274 of 803