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M16C/5L Group, M16C/56 Group
NMI Interrupt
12.9
An NMI interrupt is generated when input to the NMI pin changes state from high to low. The NMI interrupt
is a non-maskable interrupt. To use the NMI interrupt, set the PM24 bit in the PM2 register to 1 ( NMI
interrupt enabled). The NMI input uses a digital debounce function. Refer to 11. "Programmable I/O Ports"
for the digital debounce function. Figure 12.9 shows NMI Interrupt Block Diagram.
NMI
PM24: Bit in the PM2 register
NMI Interrupt Block Diagram
Figure 12.9
12.10 Key Input Interrupt
When input to any pin from P10_4 to P10_7 becomes low where the corresponding PD10_4 to PD10_7
bit in the PD10 register is 0 (input), the IR bit in the KUPIC register becomes 1 (key input interrupt
request). When using any pin from KI0 to KI3 for the key input interrupt, do not use all four pins AN4 to
AN7 as analog input pins. While input to any pin from P10_4 to P10_7 is low, inputs to all other pins of the
port are not detected as interrupts.
Key input interrupts can be used as a key-on wake up function for getting the MCU out of wait or stop
mode.
Figure 12.10 shows Block Diagram of Key Input Interrupt.
Pull-up
transistor
KI3
Pull-up
transistor
KI2
Pull-up
transistor
KI1
Pull-up
transistor
KI0
Figure 12.10 Block Diagram of Key Input Interrupt
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
NDDR register
Digital debounce filter
PU25 bit in
PUR2 register
PD10_7 bit in
PD10 register
PD10_7 bit in PD10 register
PD10_6 bit in
PD10 register
PD10_5 bit in
PD10 register
PD10_4 bit in
PD10 register
PM24
NMI interrupt
12. Interrupts
Key input
interrupt request
Page 192 of 803
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