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M16C/5L Group, M16C/56 Group
6.4.3
Power-On Reset Function
When the RESET pin is connected to VCC via a pull-up resistor, and the VCC voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets the pins,
CPU, and SFRs. Also, when a capacitor is connected to the RESET pin, always keep the voltage to the
RESET pin in the range of VIH.
When the input voltage to the VCC pin reaches Vdet0 or above, the fOCO-S count starts. When the
fOCO-S count reaches 128, the internal reset signal becomes high and the MCU executes the program
at the address indicated by the reset vector. fOCO-S divided by 8 is automatically selected as the CPU
clock after reset.
The internal RAM is not reset.
Use the voltage monitor 0 reset together with the power-on reset. Set the LVDAS bit in the OFS1
address to 0 (voltage monitor 0 reset enabled after hardware reset) to use the power-on reset. In this
case, the voltage monitor 0 reset is enabled (the VW0C0 bit and bit 6 in the VW0C register are 1 and
the VC25 bit in the VCR2 register is 1). Do not set these bits to 0 by a program.
Refer to 7. "Voltage Detector" for details of the voltage monitor 0 reset.
Figure 6.5 shows Example of Power-On Reset Operation.
V
Internal
reset signal
(low active)
Figure 6.5
Example of Power-On Reset Operation
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
V
det0
CC
V
por
t
w(por)
t
rth
1
f
OCO-S
6. Resets
× 128
Page 69 of 803
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