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REVISION HISTORY
Rev.
Date
Page
1.10 Sep. 01, 2011
523
524
535
536
537
541
545
CAN Module
550
A/D Converter
Chap. 24.
Chap. 24. 24.7.2 φ AD Frequency: Deleted.
617
620
621
622
624
625
627
629
631, 633,
635, 637
631, 633,
635, 637
640
640
640
641
Flash Memory
Chap.26. 26.10.1 Functions to Prevent Flash Memory from Being Rewritten: Deleted.
649
652
M16C/5L, M16C/56 Group User's Manual: Hardware
22.3.1.2 Bit Rate and Duty Cycle:
Added more details to the explanation of the relation between low/high period and bit rate.
22.3.1.3 Receiving a Slave Address in Wait Mode and Stop Mode: Rewritten.
Figure 22.15 Operation When Transmitted/Received a Slave Address or Data: Changed the
description of bits TRX, ADR0, and AAS in parenthesis for when a slave address is received.
Figure 22.16 Timeout Detection Timing:
• Deleted the bit descriptions in the SDAMM timing.
• Deleted "Timeout detection enabled" in the SCLMM timing.
22.3.10 Data Transmit/Receive Examples: Changed the explanation in the last paragraph.
22.3.10.5 Slave Transmission: Added an explanation for when arbitration lost is detected.
22.5.2.4 S3D0 Register and 22.5.2.6 S10 Register: Added "Use the MOV instruction to write to this
register." to the first bullet.
23.1.1 CAN0 Control Register (C0CTLR): Changed note 2 and note 3.
Changed terminologies in this chapter are as follows:
• "precharge" to "charge"
• "between execution processing time" to "inter-execution processing time"
Figure 24.1 A/D Converter Block Diagram:
• Unified upper data bus and lower data bus with a single data bus.
• Changed "Initializing cycle 2 cycles of φ AD" to "2 cycles of φ AD".
24.2.2 A/D Register i (ADi) (i = 0 to 7): Added "Read the ADi register in 16-bit units." to the register
explanation.
24.2.3 A/D Control Register 2 (ADCON2): Changed "Frequency select bit" to "Frequency select bit
2" in the Bit Name column of the CKS2 bit.
24.2.4 A/D Control Register 0 (ADCON0):
• Changed the Function column of bits CH2 to CH0.
• Changed "ADCON2" to "ADCON0" in the register explanation.
24.2.5 A/D Control Register 1 (ADCON1), Changes made to the register diagram are as follows:
• Changed the reset value from "XX00 X000b".
• Changed the Function column of SCAN1 and SCAN0.
• Changed bits b7 to b6 from "No register bits" to "Reserved bit".
24.3.1 A/D Conversion Cycle: Changed the sentence that describes selecting multiple pins.
24.3.2.2 External Trigger:
• Changed the explanation in the first paragraph.
• Added "with ADTRG " to the first bullet.
• Added Figure 24.5 A/D Conversion Start Timing When External Trigger Input.
Figure 24.6 A/D Open-Circuit Detection Example on AVCC (Preconversion Charge), Figure 24.7
A/D Open-Circuit Detection Example on AVSS (Preconversion discharge): Added the switch right
to the Analog input ANi.
Tables 24.8, 24.10, 24.12 and 24.14 for Registers and Settings:
Replaced the register diagrams with tables.
Figures 24.8 to 24.11 for Operation Example in each mode: Changed the description regarding
single A/D conversion.
24.7.1 Analog Input Pin: Changed the description.
24.7.2 Pin Configuration: Rewritten.
24.7.3 Register Access:
Changed "exclude bit 6" to "excluding the ADST bit" in line 4.
24.7.9 φ AD: Added
Table 26.2 Flash Memory Rewrite Modes Overview:
Added "CPU operating mode" and "On-board rewrite" rows.
26.3.1 Flash Memory Control Register 0 (FMR0):
Added the description for the FMR22 bit to the FMSTP bit explanation.
C- 12
Description
Summary
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