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M16C/5L Group, M16C/56 Group
18.4
Interrupts
Refer to each operation example for interrupt request occurrence timings.
Refer to 12.7 "Interrupt Control" for details on interrupt control. Table 18.19 lists Timer S Interrupt
Associated Registers.
Base timer reset request by matching the
G1BTRR register and the base timer
Base timer overflow
Channel 0
interrupt request
Channel 1
interrupt request
Channel 2
interrupt request
Channel 3
interrupt request
Channel 4
interrupt request
Channel 5
interrupt request
Channel 6
interrupt request
Channel 7
interrupt request
j = 0 to 7
G1IR0 to G1IR7: Bits in the G1IR register
G1IE00 to G1IE07: Bits in the G1IE0 register
G1IE10 to G1IE17: Bits in the G1IE1 register
Figure 18.19 Timer S Interrupt and DMA Requests
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
G1IR0
G1IE00
G1IE10
G1IR1
G1IE01
G1IE11
G1IR2
G1IE02
G1IE12
G1IR3
G1IE03
G1IE13
G1IR4
G1IE04
G1IE14
G1IR5
G1IE05
G1IE15
G1IR6
G1IE06
G1IE16
G1IR7
G1IE07
G1IE17
While the G1IRj bit selected as a source by bits G1IE0j and G1IE1j, and the
G1IRj bit is 0, when any bit from G1IR0 to G1IR7 bit is changed to 1, the IR bit
becomes 1.
18. Timer S
IC/OC base timer interrupt
(IR bit in the BTIC register)
/DMA request
IC/OC channel 0 interrupt
(IR bit in the ICOCH0IC register)
/DMA request
IC/OC channel 1 interrupt
(IR bit in the ICOCH1IC register)
/DMA request
IC/OC channel 2 interrupt
(IR bit in the ICOCH2IC register)
/DMA request
IC/OC channel 3 interrupt
(IR bit in the ICOCH3IC register)
/DMA request
IC/OC channel 4 DMA request
IC/OC channel 5 DMA request
IC/OC channel 6 DMA request
IC/OC channel 7 DMA request
IC/OC interrupt 0 request
(IR bit in the ICOC0IC register)
IC/OC interrupt 1 request
(IR bit in the ICOC1IC register)
Page 393 of 803
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