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M16C/5L Group, M16C/56 Group
2
In I
C mode, functions and timings vary depending on the IICM2 bit setting in the U2SMR2 register.
Figure 21.15 shows Transfer to U2RB Register and Interrupt Timing. See Figure 21.15 for the timing
of transferring data to the U2RB register, the bit position of the data stored in the U2RB register, types
of interrupts, interrupt requests, and DMA request generation timing.
Table 21.16 lists a comparison of other functions in clock synchronous serial I/O mode with I
2
Table 21.16
I
C Mode Functions
Function
Start and stop
condition detect
(3)
interrupts
Transmission, NACK
(2, 3)
interrupt
Reception, ACK
(2, 3)
interrupt
Timing for transferring
data from UART
reception shift register
to U2RB register
UART2 transmission
output delay
Read RXD2 and
SCL2 pin levels
Initial value of TXD2
and SDA2 outputs
Initial and end values
of SCL2
DMA1, DMA3 factor
(2)
Read received data
SMD2 to SMD0: Bits in the U2MR register
CKPOL: Bit in the U2C0 register
IICM: Bit in the U2SMR register
IICM2: Bit in the U2SMR2 register
CKPH: Bit in the U2SMR3 register
U2IRS: Bit in the U2C1 register
Notes:
1.
Set the initial value of SDA2 output while bits SMD2 to SMD0 in the UiMR register are 000b (serial interface
disabled).
2.
See Figure 21.15 "Transfer to U2RB Register and Interrupt Timing".
3.
The procedure to change interrupt sources is as follows:
(1) Disable the interrupt to be changed the source.
(2) Change the source of interrupt.
(3) Set the IR bit in the interrupt control register of that interrupt to 0 (no interrupt requested).
(4) Set bits ILVL2 to ILVL0 in the interrupt control register of that interrupt.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Clock Synchronous Serial
I/O Mode (SMD2 to SMD0
= 001b, IICM = 0 )
-
UART2 transmission
Transmission started or
completed (selected by
U2IRS)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
Possible when the
corresponding port
direction bit = 0
CKPOL = 0 (high)
CKPOL = 1 (low)
-
UART2 reception
1st to 8th bits of the
received data are stored
in bits 0 to 7 in the U2RB
register.
2
I
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 1 (Clock delay)
Start condition or stop condition detection
(See Figure 21.17 "STSPSEL Bit Functions")
No acknowledgment
detection (NACK)
Rising edge of the 9th bit of SCL2
Acknowledgment detection (ACK)
Rising edge of the 9th bit of SCL2
Rising edge of the 9th bit of SCL2
Delayed
Always possible no matter how
the corresponding port direction
bit is set
The value set in the port register
2
(1)
before setting I
C mode
Low
Acknowledgment detection (ACK)
1st to 8th bits of the received data
are stored in bits 7 to 0 in the
U2RB register.
21. Serial Interface UARTi (i = 0 to 4)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 1 (Clock delay)
UART2 transmission
Falling edge of the 9th bit of SCL2
UART2 reception
Falling edge of the 9th bit of SCL2
Falling edges of the 8th bit of
SCL2 and rising edges of the 9th
bit of SCL2
Delayed
Always possible no matter how
the corresponding port direction
bit is set
The value set in the port register
2
before setting I
C mode
Low
UART2 reception
Falling edge of the 9th bit of SCL2
Refer to Figure 21.15 "Transfer to
U2RB Register and Interrupt
Timing".
Page 471 of 803
2
C mode.
(1)
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